During its Ignite conference, Microsoft introduced a duo of custom-designed silicon made to accelerate AI and excel in cloud workloads. First of the two is Microsoft's Azure Cobalt 100 CPU, a 128-core design that features a 64-bit Armv9 instruction set, implemented in a cloud-native design that is set to become a part of Microsoft's offerings. While there aren't many details regarding the configuration, the company claims that the performance target is up to 40% when compared to the current generation of Arm servers running on Azure cloud. The SoC has used Arm's Neoverse CSS platform customized for Microsoft, with presumably Arm Neoverse N2 cores.

The next and hottest topic in the server space is AI acceleration, which is needed for running today's large language models. Microsoft hosts OpenAI's ChatGPT, Microsoft's Copilot, and many other AI services. To help make them run as fast as possible, Microsoft's project Athena now has the name of Maia 100 AI accelerator, which is manufactured on TSMC's 5 nm process. It features 105 billion transistors and supports various MX data formats, even those smaller than 8-bit bit, for maximum performance. Currently tested on GPT 3.5 Turbo, we have yet to see performance figures and comparisons with competing hardware from NVIDIA, like H100/H200 and AMD, with MI300X. The Maia 100 has an aggregate bandwidth of 4.8 Terabits per accelerator, which uses a custom Ethernet-based networking protocol for scaling. These chips are expected to appear in Microsoft data centers early next year, and we hope to get some performance numbers soon.

MediaTek today announced the Dimensity 9300, its newest flagship mobile chip with a one-of-a-kind All Big Core design. The unique configuration combines extreme performance with MediaTek's industry-leading power efficiency to deliver unmatched user experiences in gaming, video capture and on-device generative AI processing.

"The Dimensity 9300 is MediaTek's most powerful flagship chip yet, bringing a huge boost in raw computing power to flagship smartphones with our groundbreaking All Big Core design," said Joe Chen, President at MediaTek. "This unique architecture, combined with our upgraded on-chip AI Processing Unit, will usher in a new era of generative AI applications as developers push the limits with edge AI and hybrid AI computing capabilities."

The Chinese semiconductor industry is advancing, and interestingly, it is growing rapidly under sanctions, even with the blacklisting of companies by the US government. China's semiconductor industry is mainly represented by companies like Semiconductor Manufacturing International Corp (SMIC) and Huawei Technologies, who are leading the investment and progress in both chip manufacturing and chip design. According to the latest interview with Bloomberg, former TSMC Vice President Burn J. Lin said that the US government and its sanctions can not stop the advancement of Chinese semiconductor companies. Currently, Lin notes that SMIC and Huawei can use older machinery to produce more advanced chips.

Even so, SMIC could progress to 5 nm technology using existing equipment, particularly with scanners and other machinery from ASML. Development under sanctions would also force China to experiment with new materials and other chip packaging techniques that yield higher performance targets. SMIC has already developed a 7 nm semiconductor manufacturing node, which Huawei used for its latest Mate 60 Pro smartphone, based on Huawei's custom HiSilicon Kirin 9000S chip. Similarly, the transition is expected to happen to the 5 nm node as well, and it is only a matter of time before we see other nodes appear. "It is just not possible for the US to completely prevent China from improving its chip technology," noted Burn J. Lin.

Moore Threads Technology (MTT), a Chinese GPU manufacturer, is reportedly testing its next-generation graphics processors for client PCs and data centers. The products under scrutiny are the MTT S90 for client/gaming computers and the MTT S4000 for data centers. Characterized by their Device IDs, 0301 and 0323, this could imply that these GPUs belong to MTT's 3rd generation GPU lineup. While few details about these GPUs are available, the new Device IDs suggest a possible introduction of a novel microarchitecture following the MTT Chunxiao GPU series. The current generation Chunxiao series, featuring the MTT S70, MTT S80, and MTT S3000, failed to compete effectively with AMD, Intel, and NVIDIA GPUs.

Thanks to @Löschzwerg who found the Device Hunt submission, we see hardware identifiers in PCI ID and USB ID repositories earlier than launch, as this often signals the testing of new chips or drivers by various companies. In the case of MTT, the latest developments are complicated by its recent inclusion on the U.S. Entity List, limiting its access to US-made technologies. This introduces a problem for the company, as they can't access TSMC's facilities for chip production, and will have to turn to domestic production in the likely case, with SMIC being the only leading option to consider.

TSMC today announced consolidated revenue of NT$546.73 billion, net income of NT$211.00 billion, and diluted earnings per share of NT$8.14 (US$1.29 per ADR unit) for the third quarter ended September 30, 2023. Year-over-year, third quarter revenue decreased 10.8% while net income and diluted EPS both decreased 24.9%. Compared to second quarter 2023, third quarter results represented a 13.7% increase in revenue and a 16.1% increase in net income. All figures were prepared in accordance with TIFRS on a consolidated basis.

In US dollars, third quarter revenue was $17.28 billion, which decreased 14.6% year-over-year and increased 10.2% from the previous quarter. Gross margin for the quarter was 54.3%, operating margin was 41.7%, and net profit margin was 38.6%. In the third quarter, shipments of 3-nanometer accounted for 6% of total wafer revenue; 5-nanometer accounted for 37%; 7-nanometer accounted for 16%. Advanced technologies, defined as 7-nanometer and more advanced technologies, accounted for 59% of total wafer revenue.

Socionext today announced a collaboration with Arm and TSMC for the development of an innovative power-optimized 32-core CPU chiplet in TSMCʼs 2 nm silicon technology, delivering scalable performance for hyperscale data center server, 5/6G infrastructure, DPU and edge-of- network markets.

The engineering samples are targeted to be available in 1H2025. This advanced CPU chiplet proof-of-concept using Arm Neoverse CSS technology is designed for single or multiple instantiations within a single package, along with IO and application-specific custom chiplets to optimize performance for a variety of end applications.

Ever since the creation of A64FX for the Fugaku supercomputer, Fujitsu has been plotting the development of next-generation CPU design for accelerating AI and general-purpose HPC workloads in the data center. Codenamed Monaka, the CPU is the latest creation for TSMC's 2 nm semiconductor manufacturing node. Based on Armv9-A ISA, the CPU will feature up to 150 cores with Scalable Vector Extensions 2 (SVE2), so it can process a wide variety of vector data sets in parallel. Using a 3D chiplet design, the 150 cores will be split into different dies and placed alongside SRAM and I/O controller. The current width of the SVE2 implementation is unknown.

The CPU is designed to support DDR5 memory and PCIe 6.0 connection for attaching storage and other accelerators. To bring cache coherency among application-specific accelerators, CXL 3.0 is present as well. Interestingly, Monaka is planned to arrive in FY2027, which starts in 2026 on January 1st. The CPU will supposedly use air cooling, meaning the design aims for power efficiency. Additionally, it is essential to note that Monaka is not a processor that will power the post-Fugaku supercomputer. The post-Fugaku supercomputer will use post-Monaka design, likely iterating on the design principles that Monaka uses and refining them for the launch of the post-Fugaku supercomputer scheduled for 2030. Below are the slides from Fujitsu's presentation, in Japenese, which highlight the design goals of the CPU.

According to Korean business news publication ChosunBiz, both Samsung and TSMC are struggling with their 3 nm node yields. The two companies have different approaches to their 3 nm nodes, with Samsung using GAA FET (Gate All Around), whereas TSMC is continuing with its FinFET technology. That said, TSMC has at least five known 3 nm nodes, of which two should be in production by now, assuming N3E has proved to be reliable enough to kick off. Samsung on the other hand has three known 3 nm nodes, with only one in production so far, called 3GAE.

ChosunBiz reports that neither company is getting the kind of yields that you'd expect from a node that should have been in volume production for around a year by now, with Samsung apparently being somewhat better than TSMC. At 60 and 50 percent respectively, neither Samsung nor TSMC are anywhere near decent yields. Anything below 70 percent is considered very poor and even the 60 percent claim in Samsungs case, is apparently limited to some kind of Chinese mining ASIC and doesn't include the SRAM you find in most modern processors. ChosunBiz also mentions a source familiar with Samsung's foundry business who mentions a yield closer to 50 percent for the company. The same source also mentions that Samsung needs to reach at least 70 percent yield to be able to attract major customers to its 3 nm node.

AMD is preparing to launch its first APUs on the Socket AM5 desktop platform, with the Ryzen 7000G series. While the company has standardized integrated graphics with the Ryzen 7000 series, it does not consider the regular Ryzen 7000 series "Raphael" processors as APUs. AMD considers APUs to be processors with overpowered iGPUs that are fit for entry-mainstream PC gaming. As was expected for a while now, for the Ryzen 7000G series, AMD is tapping into its 4 nm "Phoenix" monolithic silicon, the same chip that powers the Ryzen 7040 series mobile processors. Proof of "Phoenix" making its way to desktop surfaced with CPU support lists for the latest AGESA SMUs (system management units) compiled by Reous, with the AGESA ComboAM5PI 1.0.8.0 listing support for "Raphael," as well as "Phoenix." Another piece of evidence was an ASUS B650 motherboard support page that listed a UEFI firmware update encapsulating 1.0.8.0, which references an "upcoming CPU."

Unlike "Raphael" and "Dragon Range," "Phoenix" is a monolithic processor die built on the TSMC 4 nm foundry node. Its CPU is based on the latest "Zen 4" microarchitecture, and features an 8-core/16-thread configuration, with 1 MB of L2 cache per core, and 16 MB of shared L3 cache. The star attraction here is the iGPU, which is based on the RDNA3 graphics architecture, meets the DirectX 12 Ultimate feature requirements, and is powered by 12 compute units worth 768 stream processors. Unlike "Raphael," the "Phoenix" silicon is known to feature an older PCI-Express Gen 4 root complex, with 24 lanes, so you get a PCI-Express 4.0 x16 PEG slot, one CPU-attached M.2 NVMe slot limited to Gen 4 x4, and a 4-lane chipset bus. "Phoenix" features a dual-channel (4 sub-channel) DDR5 memory controller, with native support for DDR5-5600. A big unknown with the Ryzen 7000G desktop APUs is whether they retain the Ryzen AI feature-set from the Ryzen 7040 series mobile processors.

TrendForce research indicates that in 1H23, the utilization rate of 8-inch production capacity primarily benefited from sporadic inventory restocking orders for Driver ICs in the second quarter. Additionally, wafer foundries initiated pricing strategies to encourage clients into early orders, offering solid backup. However, in 2H23, persistent macroeconomic and inventory challenges led to the evaporation of an anticipated demand surge.

Meanwhile, stockpiles in automotive and industrial control segments grew after meeting initial shortages, tempering demand. Under fierce price competition from PMIC leader Texas Instruments (TI), inventory reductions for Fabless and other IDMs were drastically inhibited. With IDMs ushering in output from their new plants and pulling back outsourced orders, this compounded reductions to wafer foundries. This dynamic saw 8-inch production capacity utilization dipping to 50-60% in the second half of the year. Both Tier 1 and Tier 2/3 8-inch wafer foundries saw a more lackluster capacity utilization performance compared to the first half of the year.

Intel Corporation today announced its intent to separate its Programmable Solutions Group (PSG) operations into a standalone business. This will give PSG the autonomy and flexibility it needs to fully accelerate its growth and more effectively compete in the FPGA industry, which serves a broad array of markets, including the data center, communications, industrial, automotive, aerospace and defense sectors. Intel also announced that Sandra Rivera, executive vice president at Intel, will assume leadership of PSG as chief executive officer; Shannon Poulin has been named chief operating officer.

Standalone operations for PSG are expected to begin Jan. 1, 2024, with ongoing support from Intel. Intel expects to report PSG as a separate business unit when it releases first-quarter 2024 financials. Over the next two to three years, Intel intends to conduct an IPO for PSG and may explore opportunities with private investors to accelerate the business's growth, with Intel retaining a majority stake.

Pierre Ferragu, the Global Technology Infrastructure chief at New Street Research, has predicted a very positive 2025 financial outcome for Taiwan Semiconductor Manufacturing Company Limited (TSMC). A global slowdown in consumer purchasing of personal computers and smartphones has affected a number of companies including the likes of NVIDIA and AMD—their financial reports have projected a 10% annual revenue drop for 2023. TSMC has similarly forecast that its full year revenue for 2023 will settle at $68.31 billion, after an approximate 10% fall. Ferragu did not contest these figures—via his team's analysis—TSMC is expected to pull in $68 billion in net sales for this financial year.

The rumor mill has TSMC revising its revenue guidance for a third time this year—but company leadership has denied that this will occur. New Street Research estimates that conditions will improve next year, with an uptick in client orders placed at TSMC's foundries. Ferragu reckons that TSMC could hit an all-time revenue high of $100 billion by 2025. His hunch is based on the upcoming spending habits of VIP foundry patrons encompassing: "a bottom-up perspective, looking at how TSMC's top customers, which we all know very well, will contribute to such growth." The Taiwanese foundry's order books are reported to be filling up for next year, with Apple and NVIDIA seizing the moment to stand firmly at the front of the 3 nm process queue.

TSMC today announced the new 3Dblox 2.0 open standard and major achievements of its Open Innovation Platform (OIP) 3DFabric Alliance at the TSMC 2023 OIP Ecosystem Forum. The 3Dblox 2.0 features early 3D IC design capability that aims to significantly boost design efficiency, while the 3DFabric Alliance continues to drive memory, substrate, testing, manufacturing, and packaging integration. TSMC continues to push the envelope of 3D IC innovation, making its comprehensive 3D silicon stacking and advanced packaging technologies more accessible to every customer.

"As the industry shifted toward embracing 3D IC and system-level innovation, the need for industry-wide collaboration has become even more essential than it was when we launched OIP 15 years ago," said Dr. L.C. Lu, TSMC fellow and vice president of Design and Technology Platform. "As our sustained collaboration with OIP ecosystem partners continues to flourish, we're enabling customers to harness TSMC's leading process and 3DFabric technologies to reach an entirely new level of performance and power efficiency for the next-generation artificial intelligence (AI), high-performance computing (HPC), and mobile applications."

Synopsys, Inc. today announced it is extending its collaboration with TSMC to advance multi-die system designs with a comprehensive solution supporting the latest 3Dblox 2.0 standard and TSMC's 3DFabric technologies. The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC's leading N3E process for seamless die-to-die connectivity.

"TSMC has been working closely with Synopsys to deliver differentiated solutions that address designers' most complex challenges from early architecture to manufacturing," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our long history of collaboration with Synopsys benefits our mutual customers with optimized solutions for performance and power efficiency to help them address multi-die system design requirements for high-performance computing, data center, and automotive applications."

The burgeoning AI market is significantly impacting TSMC's CoWoS (Chip on Wafer on Substrate) advanced packaging production capacity, causing it to overflow due to high demand from major companies like NVIDIA, AMD, and Amazon. To accommodate this, TSMC is in the process of expanding its production capacity by acquiring additional CoWoS machines from equipment manufacturers like Xinyun, Wanrun, Hongsu, Titanium, and Qunyi. These expansions are expected to be operational in the first half of the next year, leading to an increased monthly production capacity, potentially close to 30,000 pieces, enabling TSMC to cater to more AI-related orders. These endeavors to increase capacity are in response to the amplified demand for AI chips from their applications in various domains, including autonomous vehicles and smart factories.

Despite TSMC's active steps to enlarge its CoWoS advanced packaging production, the overwhelming client demand is driving the company to place additional orders with equipment suppliers. It has been indicated that NVIDIA is currently TSMC's largest CoWoS advanced packaging customer, accounting for 60% of its production capacity. Due to the surge in demand, companies like AMD, Amazon, and Broadcom are also placing urgent orders, leading to a substantial increase in TSMC's advanced process capacity utilization. The overall situation indicates a thriving scenario for equipment manufacturers with clear visibility of orders extending into the following year, even as they navigate the challenges of fulfilling the rapidly growing and immediate demand in the AI market.

A US delegation has visited Taiwan in order to discuss semiconductor industry partnerships—Katie Hobbs, governor of Arizona, declared that plans for TSMC's Fab 21 facility could be expanded into fairly ambitious areas: "Part of our efforts at building the semiconductor ecosystem is focusing on advanced packaging, so we have several things in the works around that right now." Bloomberg and Reuters report that she attended an important US-Taiwan supply chain forum in Taipei. Mass production at the Phoenix-area foundry has been delayed into 2025, so it is somewhat surprising to hear about greater aspirations for the site. We recently discovered that TSMC will be investing an additional $4.5 billion into its North American subsidiary, but it is too early to say whether this will finance any major upgrades.

TSMC produced a brief statement regarding the latest negotiations: "We believe the dialogues that we held during this visit will help us to work together even more closely in the future." The firm believes that the expansion of advanced chip packaging capacity will alleviate supply constraints—in the context of Taiwanese operations, at least for the moment. The Bloomberg report also focused on another delegate—Laurie E. Locascio, Under Secretary of Commerce—she announced that the North American government is starting to discuss research and development initiatives with TSMC. The key goal being to bring some of that market leading technology and knowledge stateside.

According to TechNews.tw, TSMC could postpone its 2 nm semiconductor manufacturing node for 2026. If the rumors about TSMC's delayed 2 nm production schedule are accurate, the implications could reverberate throughout the semiconductor industry. TSMC's alleged hesitancy could be driven by multiple factors, including the architectural shift from FinFET to Gate-All-Around (GAA) and potential challenges related to scaling down to 2 nm. The company is a crucial player in this space, and a delay could offer opportunities for competitors like Samsung, which has already transitioned to GAA transistor architecture for its 3 nm chips. Given the massive demand for advanced nodes due to the rise of AI, IoT, and other next-gen technologies, it is surprising to hear "sluggish" demand reports.

However, it's also possible that it's too early for customers to make firm commitments for 2025 and beyond. TSMC has dismissed these rumors, stating that construction is progressing according to plan, which includes having 2 nm pilot run in 2024, and mass production in the second half of 2025.. Despite this, any delay in TSMC's roadmap could serve as a catalyst for shifts in market dynamics. Companies that rely heavily on TSMC's advanced nodes might need to reassess their timelines and strategies. Moreover, if Samsung can capitalize on this opportunity, it could somewhat level the playing field. As of now, though, it's essential to approach these rumors with caution until more concrete information becomes available.

TSMC has gained the Taiwanese government's approval to invest $4.5 billion in its main North American manufacturing hub—Fab 21 is located in the greater Phoenix area. Mass production at the Arizona foundry has been delayed into 2025 due to behind-schedule equipment installations and various workforce-related issues, but a limited trial run is reported to begin early next year. Mid-last month, the TSMC executive board sought approval from Taiwan's Investment Commission for an additional overseas spend (the Arizona operation is registered as a subsidiary company).

This request was approved by the commission yesterday (September 18)—a $3.5 billion cash injection was already given the thumbs-up back in March. Exact areas of expenditure have not been declared to the public, but Taiwanese media outlets believe that the second phase of funds will be marked for working capital expenses at the North American division. Short-term business costs include the purchase of inventory (e.g raw materials), day-to-day operating expenses and resolvement of short-term debts. Mark Liu, TSMC's chairman, recently expressed optimism about goings-on at Arizona's Fab 21—mentioning significant progress made over the spring and summer period.

Reuters appears to be following every (internal) step that TSMC takes—their latest report suggests that company leadership has "told its major suppliers to delay the delivery of high-end chip making equipment." Two anonymous sources believe that execs are anxious about a predicted decrease in customer demand, and cost control plans have been implemented as a temporary measure. ASML is allegedly one of the vendors affected by TSMC's decision making.

Reuters conducted an interview with ASML CEO Peter Wennink a week prior—he acknowledged that some orders for high-end tools had been pushed back, without naming specific client identities, but the situation should resolve itself shortly. He stated that it was a mere "short-term management" issue: "we've had several (news) reports about fab readiness. Not only in Arizona... but also in Taiwan." ASML is reported to be operating at maximum capacity, and overall sales are forecast to grow 30% this financial year.

Mass production at TSMC's Phoenix, Arizona Fab 21 facility has been delayed until 2025, but the top brass are keen to get some activity started at their North American foundry—it is possible that they want to avoid potential contract breaches, caused by various setbacks. Taiwan's Money DJ (interpreted by TrendForce) reports that a pilot scheme will be implemented by the first quarter of 2024—industry sources believe that a small batch trial run will result in 4000 to 5000 wafer starts per month (WSPM). Setup delays have dropped projected efficiency ratings—analysts reckon that the Arizona plant cannot match the sheer effectiveness of operations back in Taiwan.

TrendForce cites a number of factors, including: "a shortage of skilled equipment installation personnel, local union protests, and differences in overseas safety regulations have caused delays in equipment installation." TSMC chairman Mark Liu expressed optimism about the situation earlier this month—citing significant progress (at the Fab 21 site) over the past five months as an early sign of success for the project. Insiders claim that TSMC is considering a major upgrade of its currently in-construction Japanese facility—extra capacity at the existing location and a second foundry could be on the table.

TSMC's Japanese facilities are set to fabricate "mature-technology chips" (28 nm and 22 nm) once construction at the site concludes next year—this $8.6 billion fab on Kyushu Island is proving to be a promising prospect for company leadership back in Taiwan. A Reuters report suggests that more ambitious plans are afoot for Japan as a key production base—two anonymous insiders claim that problems encountered at the Arizona plant have caused a shift in focus onto other global TSMC sites.

There is potential for further expansion and upgrades in Kikuyo, Kumamoto Prefecture—TSMC has reportedly taken an "increasingly optimistic view" of Japan's work culture, relatively cheap-to-build facility and a co-operative government. A smooth ramp-up of the first fabrication facility is the primary goal in 2024, but adjusted plans could add more capacity. The insiders think that a second site is also a possibility, with consideration for more advanced chip making.

Taiwan Semiconductor Manufacturing Company (TSMC) yesterday made the announcement that it has approved an investment in Arm Holdings Plc. The market leader in contract chipmaker is prepared to spend around $100 million, upon the UK-headquartered semiconductor design firm going public. Regulatory filing information has SoftBank Group aiming to raise about $4.87 billion with its initial public offering (IPO) of Arm. The listing has, so far, attracted a number of "cornerstone investors" including NVIDIA, Intel, AMD, Apple, Samsung Electronics and Alphabet.

Mark Liu, TSMC's chairman, stated last week that "Arm is an important element of our ecosystem, our technology and our customers' ecosystem. We want it to be successful, we want it to be healthy. That's the bottom line." The spending spree announcements also extended to something Team Blue related—TSMC declared that it has reached an agreement with Intel to purchase a 10% equity interest in IMS Nanofabrication Global, LLC. This deal is valued at roughly $432.8 million. Intel has already sold 20% of IMS to Bain Capital, but it still retains majority ownership—the two business deals valued IMS Nanofabrication at approximately $4.3 billion, according to an Intel statement.

Intel Corporation today announced that it has agreed to sell an approximately 10% stake in the IMS Nanofabrication business ("IMS") to TSMC. TSMC's investment values IMS at approximately $4.3 billion, consistent with the valuation of the recent stake sale to Bain Capital Special Situations ("Bain Capital"). Intel will retain majority ownership of IMS, which will continue to operate as a standalone subsidiary under the leadership of CEO Dr. Elmar Platzgummer. The transaction is expected to close in the fourth quarter of 2023.

IMS is the established industry leader in multi-beam mask writing tools required to develop advanced extreme ultraviolet lithography (EUV), which is broadly adopted in leading-edge technology nodes that enable the most demanding computing applications, such as artificial intelligence (AI) and mobile. Together, Bain Capital and TSMC's investments provide IMS with increased independence and reinforce confidence in the significant opportunity ahead of IMS. This added autonomy will help IMS accelerate its growth and drive the next phase of lithography technology innovation to enable the industry's transition into new patterning systems, such as high-numerical-aperture (high-NA) EUV.

Taiwan's Economic Daily reckons that a freshly formed partnership between TSMC, Broadcom, and NVIDIA will result in the development of cutting-edge silicon photonics. The likes of IBM, Intel and various academic institutes are already deep into their own research and development processes, but the alleged new alliance is said to focus on advancing AI computer hardware. The report cites a significant allocation of—roughly 200—TSMC staffers onto R&D involving the integration of silicon photonic technologies into high performance computing (HPC) solutions. They are very likely hoping that the usage of optical interconnects (on a silicon medium) will result in greater data transfer rates between and within microchips. Other benefits include longer transmission distances and a lower consumption of power.

TSMC vice president Yu Zhenhua has placed emphasis on innovation, in a similar fashion to his boss, within the development process (industry-wide): "If we can provide a good silicon photonics integrated system, we can solve the two key issues of energy efficiency and AI computing power. This will be a new one...Paradigm shift. We may be at the beginning of a new era." The firm is facing unprecedented demand from its clients—it hopes to further expand its advanced chip packaging capacity to address these issues by late 2024. A shift away from the limitations of "conventional electric" data transmissions could bring next generation AI compute GPUs onto the market by 2025.

TSMC Chairman Mark Liu was asked to comment on all things artificial intelligence-related at the SEMICON Taiwan 2023 industry event. According to a Nikkei Asia report, he foresees supply constraints lasting until the tail end of 2024: "It's not the shortage of AI chips. It's the shortage of our chip-on-wafer-on-substrate (COWOS) capacity...Currently, we can't fulfill 100% of our customers' needs, but we try to support about 80%. We think this is a temporary phenomenon. After our expansion of advanced chip packaging capacity, it should be alleviated in one and a half years." He cites a recent and very "sudden" spike in demand for COWOS, with numbers tripling within the span of a year. Market leader NVIDIA relies on TSMC's advanced packaging system—most notably with the production of highly-prized A100 and H100 series Tensor Core compute GPUs.

These issues are deemed a "temporary" problem—it could take around 18 months to eliminate production output "bottlenecks." TSMC is racing to bolster its native activities with new facilities—plans for a new $2.9 billion advanced chip packaging plant (in Miaoli County) were disclosed during summer time. Liu reckons that industry-wide innovation is necessary to meet growing demand through new methods to "connect, package and stack chips." Liu elaborated: "We are now putting together many chips into a tightly integrated massive interconnect system. This is a paradigm shift in semiconductor technology integration." The TSMC boss reckons that processing units fielding over one trillion transistors are viable within the next decade: "it's through packaging with multiple chips that this could be possible.".