BittWare, a Molex company, a leading supplier of enterprise-class accelerators for edge and cloud-computing applications, today introduced new card and server-level solutions featuring Intel Agilex FPGAs. The new BittWare IA-860m helps customers alleviate memory-bound application workloads by leveraging up to 32 GB of HBM2E in-package memory and 16-lanes of PCIe 5.0 (with CXL upgrade option). BittWare also added new Intel Agilex I-Series FPGA-based products with the introduction of the IA-440i and IA-640i accelerators, which support high-performance interfaces, including 400G Ethernet and PCIe 5.0 (CXL option). These newest models complement BittWare's existing lineup of Intel Agilex F-Series products to comprise one of the broadest portfolios of Intel Agilex FPGA-based offerings on the market. This announcement reinforces BittWare's commitment to addressing ever-increasing demands of high-performance compute, storage, network and sensor processing applications.

"BittWare is excited to apply Intel's advanced technology to solve increasingly difficult application problems, quickly and at low risk," said Craig Petrie, vice president, Sales and Marketing of BittWare. "Our longstanding collaboration with Intel, expertise with the latest development tools, including OneAPI, as well as alignment with Molex's global supply chain and manufacturing capabilities enable BittWare to reduce development time by 12-to-18 months while ensuring smooth transitions from proof-of-concept to volume product deployment."

Intel and MediaTek today announced a strategic partnership to manufacture chips using Intel Foundry Services' (IFS) advanced process technologies. The agreement is designed to help MediaTek build a more balanced, resilient supply chain through the addition of a new foundry partner with significant capacity in the United States and Europe. MediaTek plans to use Intel process technologies to manufacture multiple chips for a range of smart edge devices. IFS offers a broad manufacturing platform with technologies optimized for high performance, low power and always-on connectivity built on a roadmap that spans production-proven three-dimensional FinFET transistors to next-generation breakthroughs.

"As one of the world's leading fabless chip designers powering more than 2 billion devices a year, MediaTek is a terrific partner for IFS as we enter our next phase of growth," said IFS President Randhir Thakur. "We have the right combination of advanced process technology and geographically diverse capacity to help MediaTek deliver the next billion connected devices across a range of applications."

NVIDIA's next-generation GeForce RTX 4090 "Ada" flagship graphics card allegedly scores over 19000 points in the 3DMark Time Spy Extreme synthetic benchmark, according to kopite7kimi, a reliable source with NVIDIA leaks. This would put its score around 66 percent above that of the current RTX 3090 Ti flagship. The RTX 4090 is expected to be based on the 5 nm AD102 silicon, with a rumored CUDA core count of 16,384. The higher IPC from the new architecture, coupled with higher clock speeds and power limits, could be contributing to this feat. Time Spy Extreme is a traditional DirectX 12 raster-only benchmark, with no ray traced elements. The Ada graphics architecture is expected to reduce the "cost" of ray tracing (versus raster-only rendering), although we're yet to see leaks of RTX performance, yet.

Microsoft is planning a speedy launch cycle for its next-generation Windows 12 operating system, with reports pointing to a 2024 release to market. This would give Windows 11 roughly 3 years as the company's latest client OS. It could use a major release like Windows 12 to significantly change the user interface, introduce support for newer types of hardware, as well as newer APIs. At this point, Windows 12 hasn't hit any of the public Insider release cycles, so there are no hints as to what direction the OS's development is headed.

In response to rising demand for increased bandwidth of network traffic, NEXCOM, a leading supplier of network appliances, has released a compact single-port 200GbE network interface card (NIC). NL 110FM-OS leverages the award-winning NVIDIA ConnectX -6 Dx SmartNIC silicon and a PCIe Gen4 interface that doubles the speed of data transfer, compared with the previous generation PCIe standard. The network connection is enabled through one QSFP56 port to utilize double-bit PAM4 data transmission, and the NIC card is compatible with NEXCOM's latest rackmount network appliances.

The sheer volume of data traveling over the IT network leaves service providers no other choice but to adjust to the new reality. One of the ways to solve the problem is to increase the number of servers and another is to migrate to more compact solutions based on the latest technologies. The first method will require purchasing additional servers, leading to maintenance personnel expansion and energy consumption growth, whereas the second method is simply to increase the bandwidth of existing network nodes. This latter option provides a greener solution and should be preferable for all CSPs whether or not they have environmental concerns in reducing their carbon footprint.

Intel is preparing to launch its next-generation desktop platform codenamed Rocket Lake-S. According to the presentation held by Intel today in Shenzen, China, we have official information regarding some of the platform features that Raptor Lake is bringing. Starting with memory support, Raptor Lake is still carrying the transitional DDR4 and DDR5 support, as the full swing towards DDR5 is still in progress. Unlike the previous generation Alder Lake, which brought DDR5-4800 support, Raptor Lake's integrated memory controller can drive DDR5 modules with a 5600 MT/s configuration. As DDR4 support remains, it is limited to 3200 MT/s speed.

Interesting information from the leaked slide points out that support for CPU-attached NVMe storage remains PCIe Gen4. While AMD will provide an AM5 socket with CPU-attached NMVe storage on PCIe Gen5 protocol, Intel is taking a step back and holding on to Gen4. The CPU is outputting 16 PCIe Gen5 lanes on its own. Motherboard vendors for the upcoming 700-series boards for Raptor Lake can still provide a PCIe Gen5 NVMe slot; however, it will have to subtract eight Gen5 lanes from the PCI Express Graphics (PEG) slot and route them to NVMe storage. As our testing shows, this will affect GPU's performance by a few percent. AMD's upcoming AM5 platform has no such issues, as the CPU provides both the PEG and CPU-attached NVMe storage with sufficient PCIe Gen5 bandwidth.

Samsung Electronics, the world leader in semiconductor technology, today announced that it has started initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture. Multi-Bridge-Channel FET (MBCFET), Samsung's GAA technology implemented for the first time ever, defies the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability. Samsung is starting the first application of the nanosheet transistor with semiconductor chips for high performance, low power computing application and plans to expand to mobile processors.

"Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry's first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world's first 3 nm process with the MBCFET," said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. "We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology."

This time last year, I wrote about how digital experiences had never been more important, from personal to business devices - they helped us stay connected and entertained at a time when we needed it most. Compute continues to define our experiences in the modern world, and now these experiences are becoming even more visual.

Smartphones are at the center of our connected lives. From gaming to productivity, through video calling, social media or virtual environments, it is the device that provides us the connection to everyone and everything, in real time. For developers, making these immersive real-time 3D experiences even more compelling and engaging requires more performance. Arm sets the standard for performance and efficient compute, and our latest suite of compute solutions for consumer devices will continue to raise the threshold of what's possible in the mobile market, shaping the visual experiences of tomorrow.

Intel Labs announces a significant advancement in its integrated photonics research - the next frontier in increasing communication bandwidth between compute silicon in data centers and across networks. The latest research features industry-leading advancements in multiwavelength integrated optics, including the demonstration of an eight-wavelength distributed feedback (DFB) laser array that is fully integrated on a silicon wafer and delivers excellent output power uniformity of +/- 0.25 decibel (dB) and wavelength spacing uniformity of ±6.5% that exceed industry specifications.

"This new research demonstrates that it's possible to achieve well-matched output power with uniform and densely spaced wavelengths. Most importantly, this can be done using existing manufacturing and process controls in Intel's fabs, thereby ensuring a clear path to volume production of the next-generation co-packaged optics and optical compute interconnect at scale." -Haisheng Rong, senior principal engineer at Intel Labs

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today introduced the 200MP ISOCELL HP3, the image sensor with the industry's smallest 0.56-micrometer (μm)-pixels. "Samsung has continuously led the image sensor market trend through its technology leadership in high resolution sensors with the smallest pixels," said JoonSeo Yim, executive vice president of sensor business team at Samsung Electronics. "With our latest and upgraded 0.56μm 200MP ISOCELL HP3, Samsung will push on to deliver epic resolutions beyond professional levels for smartphone camera users."

Since its first 108MP image sensor roll-out in 2019, Samsung has been leading the trend of next-generation, ultra-high-resolution camera development. Through the steady launch of new image sensors and advancements in performance, the company is once again forging ahead with the 0.56μm 200MP ISOCELL HP3. The ISOCELL HP3, with a 12 percent smaller pixel size than the predecessor's 0.64μm, packs 200 million pixels in a 1/1.4" optical format, which is the diameter of the area that is captured through the camera lens. This means that the ISOCELL HP3 can enable an approximately 20 percent reduction in camera module surface area, allowing smartphone manufacturers to keep their premium devices slim.

Based on a report by the Nikkei, Japan and the US have joined forces to speed up the development of semiconductor production at 2 nm nodes in Japan by 2025. It's not exactly clear how this is going to happen, but the two nations are said to have signed a bilateral chip technology partnership. The heavy lifting is said to be done by private companies from both nations, but in terms of research and actual chip production. Part of the reason for the move, is that Japan wants to be able to manufacture cutting edge ICs domestically for next-generation chips.

The research is said to be kicking off as soon as this summer, although no decisions have been made with regards to the manufacturing structure, with the Nikkei suggesting two alternatives, based on information from the Japanese Ministry of Economy. There will either be a joint partnership between Japanese and US businesses, or it could be a wholly Japanese owned setup. It appears that one major reason for this project is the production of ICs for the Japanese defence industry, as advanced electronics are needed in a lot of related products, ranging from fighter jets and missiles, to radar systems and communication systems. However, the article also suggests that the 2 nm node is suitable for everything from components for quantum computers to smartphones. Japan already makes advanced silicon wafers and many other parts and components used in semiconductor manufacturing, but the nation has fallen behind in the actual manufacturing of leading edge semiconductors over the past few years.

AMD is planning to debut its next-generation RDNA3 graphics architecture with the Radeon RX 7000 series desktop graphics cards, some time in late-October or early-November, 2022. This, according to Greymon55, a reliable source with AMD and NVIDIA leaks. We had known about a late-2022 debut for AMD's next-gen graphics, but now we have a finer timeline.

AMD claims that RDNA3 will repeat the feat of over 50 percent generational performance/Watt gains that RDNA2 had over RDNA. The next-generation GPUs will be built on the TSMC N5 (5 nm EUV) silicon fabrication process, and debut a multi-chip module design similar to AMD's processors. The logic dies with the GPU's SIMD components will be built on the most advanced node, while the I/O and display/media accelerators will be located in separate dies that can make do on a slightly older node.

AMD in its 2022 Financial Analyst Day presentation claimed that it will repeat the over-50% generational performance/Watt uplift feat with the upcoming RDNA3 graphics architecture. This would be a repeat of the unexpected return to the high-end and enthusiast market-segments of AMD Radeon, thanks to the 50% performance/Watt uplift of the RDNA2 graphics architecture over RDNA. The company also broadly detailed the various new specifications of RDNA3 that make this possible.

To begin with, RDNA3 debuts on the TSMC N5 (5 nm) silicon fabrication node, and will debut a chiplet-based approach that's somewhat analogous to what AMD did with its 2nd Gen EPYC "Rome" and 3rd Gen Ryzen "Matisse" processors. Chiplets packed with the GPU's main number-crunching and 3D rendering machinery will make up chiplets, while the I/O components, such as memory controllers, display controllers, media engines, etc., will sit on a separate die. Scaling up the logic dies will result in a higher segment ASIC.

According to TrendForce research, North American data centers saw an improvement in components supply after February, driving a recovery in purchase order volume. As Server brands returned to normal in-office work following the pandemic, the increase in capital expenditures on related information equipment has also boosted order growth. The addition of Kioxia's raw material contamination incident led to an increase in the pricing of certain rush orders, pushing up overall Enterprise SSD revenue in 1Q22 to US$5.58 billion, or 14.1% growth QoQ.

According to TrendForce, Samsung and SK hynix (including Solidigm) were the top two players in 1Q22. At the beginning of the year, demand from hyperscale data centers resulted in high inventory levels due to component mismatches, leading Samsung's order growth missing expectations. However, as repercussions from the WDC and Kioxia contamination incident hit NAND Flash production capacity in 1Q22, server customers quickly turned to Samsung for additional orders, driving the company's 1Q22 revenue to US$2.77 billion, up 14.8% QoQ.

AMD's upcoming Radeon RX 7000 series of graphics cards based on the RDNA 3 architecture are supposed to feature next-generation protocols all over the board. Today, according to a patch committed to the Linux kernel, we have information about display output choices AMD will present to consumers in the upcoming products. According to a Twitter user @Kepler_L2, who discovered this patch, we know that AMD will bundle DisplayPort 2.0 technology with UHBR 20 transmission mode. The UHBR 20 standard can provide a maximum of 80 Gbps bi-directional bandwidth, representing the highest bandwidth in a display output connector currently available. With this technology, a sample RDNA 3 GPU could display 16K resolution with Display Stream Compression, 10K without compression, or two 8K HDR screens running at 120 Hz refresh rate. All of this will be handled by Display Controller Next (DCN) engine for media.

The availability of DisplayPort 2.0 capable monitors is a story of its own. VESA noted that they should come at the end of 2021; however, they got delayed due to the lack of devices supporting this output. Having AMD's RDNA 3 cards as the newest product to support these monitors, we would likely see the market adapt to demand and few available products as the transition to the latest standard is in the process.

Nintendo could release its next-generation handheld game console, a successor to the crazy-popular Switch, by 2024. This could be powered by an NVIDIA-sourced SoC. NVIDIA recently put up a job listing for a "Game Console Developer Tools Engineer," looking for talent designing the software development applications for the next-generation console. Nintendo is a long-standing customer of NVIDIA chips for its handheld consoles. The next-gen SoC could implement an NVIDIA-designed Arm CPU, and a highly efficient GPU based on the NVIDIA graphics architecture of the time.

Today we got information that AMD's upcoming Instinct MI300 will be allegedly available as an Accelerated Processing Unit (APU). AMD APUs are processors that combine CPU and GPU into a single package. AdoredTV managed to get ahold of a slide that indicates that AMD Instinct MI300 accelerator will also come as an APU option that combines Zen4 CPU cores and CDNA3 GPU accelerator in a single, large package. With technologies like 3D stacking, MCM design, and HBM memory, these Instinct APUs are positioned to be a high-density compute the product. At least six HBM dies are going to be placed in a package, with the APU itself being a socketed design.

The leaked slide from AdoredTV indicates that the first tapeout is complete by the end of the month (presumably this month), with the first silicon hitting AMD's labs in Q3 of 2022. If the silicon turns out functional, we could see these APUs available sometime in the first half of 2023. Below, you can see an illustration of the AMD Instinct MI300 GPU. The APU version will potentially be of the same size with Zen4 and CDNA3 cores spread around the package. As Instinct MI300 accelerator is supposed to use eight compute tiles, we could see different combinations of CPU/GPU tiles offered. As we await the launch of the next-generation accelerators, we are yet to see what SKUs AMD will bring.

The Video Electronics Standards Association (VESA ) today announced that the first video source and display devices supporting DisplayPort UHBR (Ultra-high Bit Rate) - the higher data link rates supported by the DisplayPort standard version 2.0 - have completed certification through the DisplayPort UHBR Certification Program. To achieve this important milestone, UHBR chipset reference source and display designs provided by AMD, MediaTek and Realtek successfully met the PHY, link and interoperability testing requirements outlined in the DisplayPort 2.0 Compliance Test Specification (CTS). The higher bandwidths enabled by UHBR support a variety of use cases such as uncompressed 8K 60 Hz HDR, 4K 240 Hz HDR, two 4K 120 Hz HDR or four 4K 60 Hz HDR displays through a single cable.

VESA also announced today that qualified VESA DisplayPort Authorized Test Centers (ATCs) are ready to begin testing and certification of UHBR end-products using approved test equipment and reference sink and source devices for interoperability testing. An engineering demonstration of a reference source and sink device setup from AMD and MediaTek operating at UHBR link rates will be showcased at the Display Week Symposium and Exhibition in San Jose, Calif., on May 10-12, 2022 at VESA booth #214 at the San Jose Convention Center.

Porotech, a pioneer in micro-LED and GaN-based semiconductor material technology, will be unveiling DynamicPixelTuning on its PoroGaN microdisplay platform at the Display Week event in California next week. The breakthrough makes it possible to create full-colour or tuneable-colour displays using identical pixels from a single wafer - achieving colour uniformity, while eliminating complex fabrication processes. The innovation is set to accelerate the commercialisation of micro-LEDs, mini-LEDs and LEDs to deliver next-generation display products for AR/MR/VR applications, smart wearable devices, smart displays and large-scale direct view displays.

Porotech is the first in the world to unlock dynamic colour tuning of LED chips and pixels. Its PoroGaN platform makes it possible for each individual tiny LED on an epiwafer to emit all colours of the visible spectrum. At this stage, the Porotech proof-of-concept displays are tuneable monocolour, with uniform brightness and colour for display products in the micro (µm) and nano (nm) pixel space. But the company's proprietary PoroGaN platform and Dynamic Pixel technology are paving the way to a monolithic full-colour RGB display very soon.

Comcast, the nation's largest gig-speed Internet provider, today demonstrated the fastest-yet speeds it has achieved over a complete 10G connection on a live network, reaching download speeds faster than 8 gigabits per second (Gbps) and upload speeds faster than 5 Gbps. At an industry 10G event at CableLabs headquarters, Comcast also showed the 10G node technology that will help power its deployments and demonstrated how its network virtualization technology will seamlessly orchestrate mixed fiber and 10G deployments. 10G is the technology that will enable Comcast and other network operators to deliver multigigabit symmetrical speeds - combined with improved latency, security, and reliability - over the connections already installed in tens of millions of homes and businesses worldwide.

For the demo, Comcast connected a 10G-enabled Virtualized Cable Modem Termination System (vCMTS) linked by more than 80 kilometers of fiber to the demonstration site. The fiber terminated into a production switch, which connected to what is believed to be the world's first fully functional 10G-enabled Full Duplex DOCSIS 4.0 node, along with a 10G prototype modem at CableLabs headquarters. Today's demonstration is a first in a production-ready network environment, showing how live 10G deployments will work, orchestrated by Comcast's Distributed Access Architecture (DAA) technology, which is already widely deployed.

Ayar Labs, the leader in chip-to-chip optical connectivity, today announced that the company has secured $130 million in additional financing led by Boardman Bay Capital Management to drive the commercialization of its breakthrough optical I/O solution. Hewlett Packard Enterprise (HPE) and NVIDIA entered this investment round, joining existing strategic investors Applied Ventures LLC, GlobalFoundries, Intel Capital, and Lockheed Martin Ventures. Other new strategic and financial investors participating in the round include Agave SPV, Atreides Capital, Berkeley Frontier Fund, IAG Capital Partners, Infinitum Capital, Nautilus Venture Partners, and Tyche Partners. They join existing investors such as BlueSky Capital, Founders Fund, Playground Global, and TechU Venture Partners.

"As a successful technology-focused crossover fund operating for over a decade, Ayar Labs represents our largest private investment to date," said Will Graves, Chief Investment Officer at Boardman Bay Capital Management. "We believe that silicon photonics-based optical interconnects in the data center and telecommunications markets represent a massive new opportunity and that Ayar Labs is the leader in this emerging space with proven technology, a fantastic team, and the right ecosystem partners and strategy."

With the release of Hopper, NVIDIA's cycle of new architecture releases is not yet over. Later this year, we expect to see next-generation gaming architecture codenamed Ada Lovelace. According to a well-known hardware leaker for NVIDIA products, @kopite7kimi, on Twitter, the green team is reportedly testing a potent variant of the upcoming AD102 SKU. As the leak indicates, we could see an Ada Lovelace AD102 SKU with a Total Graphics Power (TGP) of 900 Watts. While we don't know where this SKU is supposed to sit in the Ada Lovelace family, it could be the most powerful, Titan-like design making a comeback. Alternatively, this could be a GeForce RTX 4090 Ti SKU. It carries 48 GB of GDDR6X memory running at 24 Gbps speeds alongside monstrous TGP. Feeding the card are two 16-pin connectors.

Another confirmation from the leaker is that the upcoming RTX 4080 GPU uses the AD103 SKU variant, while the RTX 4090 uses AD102. For further information, we have to wait a few more months and see what NVIDIA decides to launch in the upcoming generation of gaming-oriented graphics cards.

Our first-quarter net sales came in at €3.5 billion which is at the high end of our guidance. The gross margin of 49.0%, is as guided. Our first-quarter net bookings came in at €7.0 billion, including €2.5 billion from 0.33 NA and 0.55 NA EUV systems as well as very strong DUV bookings, reflecting the continued high demand for advanced and mature nodes.

"We continue to see that the demand for our systems is higher than our current production capacity. We accommodate our customers through offering high-productivity upgrades and reducing cycle time in our factories, and we continue to offer a fast shipment process. In addition, we are actively working to significantly expand capacity together with our supply chain partners. In light of the demand and our plans to increase capacity, we expect to revisit our scenarios for 2025 and growth opportunities beyond. We plan to communicate updates in the second half of the year.

Everyone's favorite GPU-news leaker Kopite7kimi has updated his tweet from April 1 with more specific board part numbers, and suddenly the information contained there—which could have been misinterpreted as an April 1st joke—now all seems to add up with our own posting from last month about memory bus widths. The update seems to indicate the boards will now feature 21 Gbps memory, which is the same as what we saw on the recently made available RTX 3090 Ti cards, and Videocardz goes further to speculate the 3090 Ti could have been a dry run for the upcoming cards, including with a similar 600 W TDP rating to follow. Note also that the leaker is shying away from referring to these as the RTX 4080/4090 series, leaving room in case NVIDIA decides to jump in naming scheme for reasons including marketing and what the competition decides.

ERS electronic, the industry leader in the market of thermal management solutions for semiconductor manufacturing, reveals the details of its third-generation flagship thermal debond machine, ADM330. The machine was introduced to the market in 2007 as the first-of-its-kind. Since then, it has become an industry-favourite and can be found on the production floors of most semiconductor manufacturers and OSATs involved in Advanced Packaging worldwide.
Earlier this month, the company was recognized for its continuous innovation and contribution to heterogeneous integration technologies with a 3D InCites "Equipment Supplier of the Year" award.

ERS is now giving a first look at the next-generation ADM330, which has changed its previously matte metallic appearance to a clean, white surface matching most equipment found in a cleanroom. In addition, the machine is now fully compliant with the GEM300 SEMI standards, thus allowing seamless integration into automated fabs and Industry 4.0 architectures. Warpage adjustment performance has also been improved thanks to a unique thermal chuck design that enables a strong vacuum performance three times better than its predecessor. Lastly, the new ADM330 offers an implemented add-on software feature allowing stand-alone laser marking for improved wafer traceability.