Tuesday, October 31st 2017

Purdue University Develops Next-Gen, 3D Intrachip Cooling Technology

Researchers based on Purdue University have designed an intrachip cooling technology, which will likely pave the way for future generations of high performance 3D microprocessors. The research was part of a DARPA-funded commission for Purdue University's Birck Nanotechnology Center; a fundamental requirement stipulated by DARPA was the ability for this cooling system to handle chips generating 1 kW of heat per cm², more than 10x the amount current high-performance computers generate.

The new cooling system circulates an electrically insulated liquid coolant directly into electronic chips through an intricate series of tiny microchannels. This means that no longer will cooling systems be limited to the nowadays-employed conventional chip-cooling methods, which make use of finned metal plates called heat sinks. These are attached to computer chips to dissipate heat, but have a fundamental flaw: they do not remove heat efficiently enough for an emerging class of high-performance, 3D electronics, where too much heat hinders the performance of electronic chips or damages the tiny circuitry, especially in small "hot spots" that are located below the topmost layer of the chip.
"You can pack only so much computing power into a single chip, so stacking chips on top of each other is one way of increasing performance," said Justin A. Weibel, a research associate professor in Purdue's School of Mechanical Engineering, and co-investigator on the project. "This presents a cooling challenge because if you have layers of many chips, normally each one of these would have its own system attached on top of it to draw out heat. As soon as you have even two chips stacked on top of each other the bottom one has to operate with significantly less power because it can't be cooled directly."
Suresh V. Garimella, who is principal investigator for the project and the Goodson Distinguished Professor of Mechanical Engineering at Purdue University, added that "This transformative approach has great promise for use in radar electronics, as well as in high-performance supercomputers. In this paper, we have demonstrated the technology and the unprecedented performance it provides."

The system uses a commercial refrigerant called HFE-7100, a dielectric, or electrically insulating fluid, meaning it won't cause short circuits in the electronics. As the fluid circulates over the heat source, it boils inside the microchannels, somewhat like current vapor-chamber technology - but multiplied by X.
"Allowing the liquid to boil dramatically increases how much heat can be removed, compared to simply heating a liquid to below its boiling point," said Garimella. To increase efficiency and reduce pressure drops associated with long cooling channels that cover the length of the chip to be cooled, the team opted for a system of short, parallel channels, where a "hierarchical" manifold distributes the flow of coolant. "So, instead of a channel being 5,000 microns in length, we shorten it to 250 microns long," Garimella added. "The total length of the channel is the same, but it is now fed in discrete segments, and this prevents major pressure drops. So this represents a different paradigm." Sources: Purdue NewsRoom, via Hexus
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16 Comments on Purdue University Develops Next-Gen, 3D Intrachip Cooling Technology

#1
MyTechAddiction
sounds awesome , however I see no mention of what happens on the heat dissipation part? Will it have a refrigerator style radiator as well?
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#2
P4-630
The Way It's Meant to be Played
Sooo... When can we see this in laptops!? :D:D
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#3
laszlo
at that scale will be a challenge to create a closed circuit for the coolant ; design is nice but is still on paper...
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#4
Mirkoskji
Every new breaktrhough in computing solutions, in the last few years, goes further away from consumer feasibility. Even if you could get a 1kw chip to be sufficiently cooled by this system plus an external heatsink, they're still 1000w of power. Anyway, i like the concept and I also think that the moment a chip like a CPU will be stacked in design, then it will integrate HBM without the need of an interposer. So HBM solutions may become cheaper and more feasible, even a new form of integrated cache in the GPU/CPU.
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#5
RejZoR
Main problem we're facing is heat concentration. As we're shrinking down chips and cramming more transistors into them, the more power they consume and the more heat they generate on smaller surface. What's real challenge is taking away that heat efficiently from such tiny surface. That's the real problem, not heat itself.

I mean, if you have to take heat away 200W of heat from a chip the size of 5x5mm or same amount from the chip the size of 20x20mm, I think I don't have to further explain what we're facing here. We have coolers more than capable of dealing even with 16 core CPU's without much trouble, the problem is, they are really tiny. And AMD's approach of multiple dies and cores connected with Infinity Fabric is in a way having an edge over Intel's tiny monolithic designs. The heat output may be the same, but AMD has an easier way of managing it thanks to larger surface area.
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#6
ZeppMan217
So what happens if a microchannel bursts and the coolant leaks out?
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#7
Basard
MyTechAddiction said:
sounds awesome , however I see no mention of what happens on the heat dissipation part? Will it have a refrigerator style radiator as well?
Giant heat sink sitting on top of it all.. lol.
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#8
FR@NK
I've used that novec fluid for submersion cooling and it works alright but the heat transfer properties are afew multiples worse compared to water based coolants.
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#9
OSdevr
To me this sounds a lot like they put heat pipes into the chip structure itself. It doesn't eliminate the heat sink it just moves it, but like heat pipes in a heat sink it will keep the chip cooler as long as you can exhaust the heat somewhere else.
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#10
v12dock
Reminds me of Intel's Tejas architecture which targeted super high frequencies on a 40-50 stage pipeline. I think one of Intel engineers came out and said heat was such an impossible task to deal with and it would be some sort of similar technology to this do deal with the heat.
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#13
Beertintedgoggles
Boosnie said:
Less beer, more reading

https://www.purdue.edu/newsroom/releases/2017/Q4/purdue-develops-intrachip-micro-cooling-system-for-high-performance-radar,-supercomputers---.html
Maybe others can help me out but it sure appears that IBM already did this back in 2008. The only differences I can see are the dimension of the microchannels and their distribution layout (the manifold).

Here is the article I quoted by Mark Lepedus:

BURLINGAME, Calif. -- IBM, Georgia Institute of Technology and Nanonexus presented a technology that involves 3D devices with integrated microchannel cooling.
In a paper, the companies claimed to have demonstrated a 3D silicon die with a density of 2500/cm2 -- and integrated with microchannel heat sinks.
With the technology, a microchanneled cooled processor at 3-GHz can operate at 83 Watts in 47 degree Celsius conditions, according to the paper. In comparison, an air cooled processor at 3-GHz operates at 102 Watts in 88 degree Celsius conditions, according to the paper.
The technology involves a 3D stacking technique called through-hole vias (TSVs). The problem with TSVs is to remove the heat in 3D structures, especially in microprocessor designs, said Deepak Sekar, an engineer at SanDisk Corp., who presented the paper at the IEEE 2008 International Interconnect Technology Conference (IITC) here this week.
''When two 100W/cm2 microprocessors are stacked on top of each other, for example, the net power density becomes 200W/cm2 and is beyond the heat removal limits of currently available air cooling technology,'' Sekar said in the paper.
The paper proposes the idea of fabricating TSVs on a wafer. First, a chip is fabricated. Second, the chip is etched to form the fluidic TSVs and microchannels. This is a two-step lithography process.
Third, the device is spin coated and polished with a sacrificial polymer material. Then, the polymer is spun-on, patterned and cured to form a cover for the TSVs and microchannels.
The microchannels are said to be 200-um tall and 150-um wide. The copper TSVs are 50-um in diameter. Silicon thickness is 400-um, while copper density is said to be 2500/cm2, according to the paper.
"Cooling fluid can be delivered to the 3D stack either using tubes on the back side of the 3D stack or using fluidic channels on the substrate,'' he said. ''The fluid is then delivered to the microchannel heat sinks on the back side of each chip in the 3D stack using fluidic through silicon vias and fluidic pipes.''
A two-chip 3D stack is said to show a junction-to-ambient thermal resistance of 0.24 degrees Celsius per Watt, according to the paper.
Chip scaling is showing no signs of hitting the wall--yet. But one alternative path--3D technology based on TSVs--continues to generate steam.
TSV technology took center stage at the IEEE 2008 International Interconnect Technology Conference (IITC) here this week. Georgia Institute of Technology, IBM, IMEC, Fraunhofer, Tohoku University, TSMC and others presented papers on TSV at IITC, although there is still no consensus just how the industry will bring the long-awaited technology into the mainstream.


Some more info on the topic published in 2014 : http://www.rit.edu/kgcoe/mechanical/taleme/Papers/Journal%20Papers/J141.pdf
Posted on Reply
#14
Boosnie
Beertintedgoggles said:
Maybe others can help me out but it sure appears that IBM already did this back in 2008. The only differences I can see are the dimension of the microchannels and their distribution layout (the manifold).

Here is the article I quoted by Mark Lepedus:

BURLINGAME, Calif. -- IBM, Georgia Institute of Technology and Nanonexus presented a technology that involves 3D devices with integrated microchannel cooling.
In a paper, the companies claimed to have demonstrated a 3D silicon die with a density of 2500/cm2 -- and integrated with microchannel heat sinks.
With the technology, a microchanneled cooled processor at 3-GHz can operate at 83 Watts in 47 degree Celsius conditions, according to the paper. In comparison, an air cooled processor at 3-GHz operates at 102 Watts in 88 degree Celsius conditions, according to the paper.
The technology involves a 3D stacking technique called through-hole vias (TSVs). The problem with TSVs is to remove the heat in 3D structures, especially in microprocessor designs, said Deepak Sekar, an engineer at SanDisk Corp., who presented the paper at the IEEE 2008 International Interconnect Technology Conference (IITC) here this week.
''When two 100W/cm2 microprocessors are stacked on top of each other, for example, the net power density becomes 200W/cm2 and is beyond the heat removal limits of currently available air cooling technology,'' Sekar said in the paper.
The paper proposes the idea of fabricating TSVs on a wafer. First, a chip is fabricated. Second, the chip is etched to form the fluidic TSVs and microchannels. This is a two-step lithography process.
Third, the device is spin coated and polished with a sacrificial polymer material. Then, the polymer is spun-on, patterned and cured to form a cover for the TSVs and microchannels.
The microchannels are said to be 200-um tall and 150-um wide. The copper TSVs are 50-um in diameter. Silicon thickness is 400-um, while copper density is said to be 2500/cm2, according to the paper.
"Cooling fluid can be delivered to the 3D stack either using tubes on the back side of the 3D stack or using fluidic channels on the substrate,'' he said. ''The fluid is then delivered to the microchannel heat sinks on the back side of each chip in the 3D stack using fluidic through silicon vias and fluidic pipes.''
A two-chip 3D stack is said to show a junction-to-ambient thermal resistance of 0.24 degrees Celsius per Watt, according to the paper.
Chip scaling is showing no signs of hitting the wall--yet. But one alternative path--3D technology based on TSVs--continues to generate steam.
TSV technology took center stage at the IEEE 2008 International Interconnect Technology Conference (IITC) here this week. Georgia Institute of Technology, IBM, IMEC, Fraunhofer, Tohoku University, TSMC and others presented papers on TSV at IITC, although there is still no consensus just how the industry will bring the long-awaited technology into the mainstream.


Some more info on the topic published in 2014 : http://www.rit.edu/kgcoe/mechanical/taleme/Papers/Journal Papers/J141.pdf
I read it.
But a monorail is, in fact, a train. So I dismiss It as a 200 years old tech.
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#15
Beertintedgoggles
Unfortunately I'm going to have to assume a little in understanding what you are trying to say. I think you are pointing out the fact that a monorail can be considered a train even though the original train tech is old. I don't quite see the analogy here. The Purdue team created microchannels in the silicon between the substrate layers and used a non-conductive coolant piped through them. That is exactly what IBM started back in 2008. The Rochester Institute of Technology paper from 2014 also credited IBM with their work. I didn't see one mention of IBM in the Purdue paper. Claiming Purdue developed this next-gen technology is like saying Apple invented the mp3 player.
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#16
StrayKAT
Sometimes I'm reminded how primitive our machines really are. Our cooling mechanisms, both mechanical and NAND drives, etc.. We're barely better than cavemen. :p
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