Report an Error

Intel Celeron 1300

1
Cores
1
Threads
33 W
TDP
1300 MHz
Frequency
N/A
Boost
Tualatin
Codename
Socket 370
Socket
Intel Socket 370
Intel Socket 370
The Intel Celeron 1300 was a desktop processor with 1 core, launched in January 2002, at an MSRP of $118. It is part of the Celeron lineup, using the Tualatin architecture with Socket 370. Celeron 1300 has 256 KB of L2 cache and operates at 1300 MHz. Intel is making the Celeron 1300 on a 130 nm production node using 44 million transistors. The multiplier is locked on Celeron 1300, which limits its overclocking potential.
With a TDP of 33 W, the Celeron 1300 consumes only little energy. The highest officially supported memory speed is 133 MT/s, but with overclocking (and the right memory modules) you can go even higher. Actual memory technology support depends on the chosen motherboard, because the memory controller is located on the motherboard (not in the processor). Although the processor doesn't come with integrated graphics, certain motherboards with compatible chipsets can provide this capability.
Many games will refuse to start on this processor due to the lack of the SSE2/SSE3/SSE4 instruction set.

Physical

Socket: Intel Socket 370
Foundry: Intel
Process Size: 130 nm
Transistors: 44 million
Die Size: 80 mm²
Package: µPGA
tCaseMax: 70°C

Processor

Market: Desktop
Production Status: End-of-life
Release Date: Jan 3rd, 2002
Launch Price: $118
Part#: SL5VR
SL5ZJ
SL6C7
SL6JT

Performance

Frequency: 1300 MHz
Turbo Clock: N/A
Base Clock: 100 MHz
Multiplier: 13.0x
Multiplier Unlocked: No
Voltage: 1.5 V
TDP: 33 W

Architecture

Codename: Tualatin
Generation: Celeron
(Tualatin)
Memory Support: unknown
Depends on motherboard
Rated Speed: 133 MT/s
Memory Bus: Single-channel
Northbridge Location: Motherboard
ECC Memory: No
Chipsets: i815, i815e, VIA 694T, ALi M1651T, SiS 635T

Core Config

# of Cores: 1
# of Threads: 1
SMP # CPUs: 1
Integrated Graphics: On certain motherboards (Chipset feature)

Cache

Cache L1: 32 KB
Cache L2: 256 KB

Features

  • MMX
  • SSE

Notes

Many S-Specs overlap in stepping code. Stepping table is as follows:

Stepping A0 - SL5VR, SL5ZJ, SL6JT
Stepping A3 - SL5VR
Stepping B1 - SL6C7, SL6JT
Stepping BA - SL6C7
Jun 15th, 2024 17:52 EDT change timezone

New Forum Posts

Popular Reviews

Controversial News Posts