imperialreign
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jumping in late to the "argument" but would like to offer some thoughts
yes, GDDR5 will prob call for extremelly high latencies, as did GDDR4 when compared to GDDR3, and GDDR3 when compared to GDDR2
but what you forget to take into account is that GDDR5 should be able to move more information per clock cycle, like GDDR4 when compared to GDDR3, and GDDR3 when compared to GDDR2
what that translates to - is higher latencies, but more information being transferred - which null and voids any drawbacks with having to run higher latencies.
and coupled with the fact that newer memory desgins allow for higher clocked MEM, require less voltage - that makes them more efficient compared to their predecessors.
Just like with SYS MEM - DDR3 can move more information than DDR2 can, and runs faster as well. Sure, it's possible that DDR2 clocked at 1200 will run 51ms latencies, but so can DDR3 at 1600MHz . . . and which standard transfers more information? The more information that can be moved into and out of the DRAM matrix per clock cycle means the less amount of time you're sitting waiting for things to load up.
yes, GDDR5 will prob call for extremelly high latencies, as did GDDR4 when compared to GDDR3, and GDDR3 when compared to GDDR2
but what you forget to take into account is that GDDR5 should be able to move more information per clock cycle, like GDDR4 when compared to GDDR3, and GDDR3 when compared to GDDR2
what that translates to - is higher latencies, but more information being transferred - which null and voids any drawbacks with having to run higher latencies.
and coupled with the fact that newer memory desgins allow for higher clocked MEM, require less voltage - that makes them more efficient compared to their predecessors.
Just like with SYS MEM - DDR3 can move more information than DDR2 can, and runs faster as well. Sure, it's possible that DDR2 clocked at 1200 will run 51ms latencies, but so can DDR3 at 1600MHz . . . and which standard transfers more information? The more information that can be moved into and out of the DRAM matrix per clock cycle means the less amount of time you're sitting waiting for things to load up.