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Intel 14 nm Node Compared to TSMC's 7 nm Node Using Scanning Electron Microscope

AleksandarK

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Currently, Intel's best silicon manufacturing process available to desktop users is their 14 nm node, specifically the 14 nm+++ variant, which features several enhancements so it can achieve a higher frequencies and allow for faster gate switching. Compare that to AMD's best, a Ryzen 3000 series processor based on Zen 2 architecture, which is built on TSMC's 7 nm node, and you would think AMD is in clear advantage there. Well, it only sort of is. German hardware overclocker and hacker, der8auer, has decided to see how one production level silicon compares to another, and he put it to the test. He decided to use Intel's Core i9-10900K processor and compare it to AMD's Ryzen 9 3950X under a scanning electron microscope (SEM).

First, der8auer took both chips and detached them from their packages; then he proceeded to grind them as much as possible so SEM could do its job of imaging the chips sans the substrate and protective barrier. This was followed by securing the chips to a sample holder using an electrically conductive adhesive to improve penetration of the high energy electrons from the SEM electron gun. To get as fair a comparison as possible, he used the L2 cache component of both processors as they are usually the best representatives of a node. This happens because the logic portion of the chip differs according to architecture; hence, level two cache is used to get a fair comparison - it's design is much more standardized.





The results? Well, the Intel 14 nm chip features transistors with a gate width of 24 nm, while the AMD/TSMC 7 nm one has a gate width of 22 nm (gate height is also rather similar). While these are not much different, TSMC's node is still much denser compared to Intel's - TSMC's 7 nm produces chips with a transistor density around 90 MT/mm² (million transistors per square millimeter), which is comparable in density to Intel's 10 nm node used on recent mobile processors. Below you can see the SEM images and comparison made. For more information and details please head over to the source.

Another interesting thing to note here, the gate width is not following the naming scheme as you might have expected. The 14 nm transistor isn't 14 nm in width, and the 7 nm transistor isn't 7 nm wide. The naming of the node and actual size of the node have had a departure a long time ago, and the naming convention is really up to the manufacturer - it's become more of a marketing gimmick than anything else. This is the reason researchers have already proposed another density metric for semiconductor technology other than pure "nm" terms.

View at TechPowerUp Main Site
 
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Looks like we have a long way to go still then, if we're actually at around 2xnm rather than something much smaller...
 
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We are at a point when advances diminishes and price increases exponentially with each silicon node shrink.

Time to advance in to new materials to get the shrinking going again for real and even get the cost down in the long run.

Today's prices making silicon at 5nm is ridiculous and 3nm will be insane.

All these super computers trying to figure out tomorrows weather should be put to work trying to figure out new materials for making chips instead.
 
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X-Ray images? I know that X-rays can be/are produced during this, but i thought this works by reflection and refraction of electrons... huh
 
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Probably time to dump silicon for new material.
Like GaN? It's not suitable for a lot semiconductors though, hence why it's used more in niche cases.
 

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Benchmark Scores I once had +100 dorfs in DF, so yeah pretty great
Yeah what is beyond silicone is a huge question, and afaik there are no clear/good answers.
 
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These + suffixes improve the power gradient for Intel at each incremental stepping, so the benchmark should continue on with transistor switching benchmarks, imho.
TL;DR Intel is still competitive on the power gating front.
 
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Yeah what is beyond silicone is a huge question

Not much, there are some prospects for achieving higher frequencies/efficiency in other material but as far as component density, that's over. They are literally running out of atoms, 3D stacking is going to be the only way to increase density and that comes with a heap of problems as well.
 
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"The naming of the node and actual size of the node departure a long time ago"

Proof reading please.
 
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Not much, there are some prospects for achieving higher frequencies/efficiency in other material but as far as component density, that's over. They are literally running out of atoms, 3D stacking is going to be the only way to increase density and that comes with a heap of problems as well.

If Intel play their advantage on 3D stacking right, they can potentially win the long game.
 
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If Intel play their advantage on 3D stacking right, they can potentially win the long game.
I've heard over the years that 3D is not in competition with 2.5D. Also, heat pockets are phenomenal.
 
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Looks like we have a long way to go still then, if we're actually at around 2xnm rather than something much smaller...

Didn't we know this already? Intel's density was always much higher on the recent nodes. Its really all dependant on what metric you want to look at. TSMC 7nm still has other advantages over 14nm besides the gate width though.

We kinda knew this since Ivy Bridge, 22nm, when increased heat concentration would put pressure on the IHS/TIM solution, neutering OC potential. Ever since AMD adopted 7nm for its CPUs, they're seeing similar stuff.

Nonetheless its nice to see it from this angle and with the current state of things, seeing as Intel added all those pluses.

The TL DR here is that over the past half decade, in spite of glorious marketing, the best we can say is we've made a tiny baby step forward from 14nm's first iteration. Sounds depressing if you think of the artillery that was used to get here... OTOH, it also means we've still got ground to cover.

" And it kind of it " Proof Reading

"The naming of the node and actual size of the node departure a long time ago"

Proof reading please.

You think this is bad? Lol. Welcome to TPU. Get used to it;)
Next time if you want corrections its a better idea to send the poster a PM or tag them in your reply with @
 
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If the difference in node pitch is so tiny, this just means that AMD's desktop designs are just this much better than Intel's desktop (power and performance per area), and that Intel is still ahead in laptops and possibly servers once IceLake-SP is released.
 
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This is very interesting. It's always the marketing that has to make things more complicated and confusing.
In the end what really matters is performance per Watt.
 
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This is very interesting. It's always the marketing that has to make things more complicated and confusing.
In the end what really matters is performance per Watt.
If you say that, Intel has equivalency. TSMC is ahead in extra features.
 
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You think this is bad? Lol. Welcome to TPU. Get used to it;)
Next time if you want corrections its a better idea to send the poster a PM or tag them in your reply with @
Still better than a lot of other sites that don't even bother fixing their mistakes. A news site I read mixed up Nepal and Naples and never bothered to fix it...
 
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Still better than a lot of other sites that don't even bother fixing their mistakes. A news site I read mixed up Nepal and Naples and never bothered to fix it...

I suppose they're both above sea level? LOL
 
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Looks like we have a long way to go still then, if we're actually at around 2xnm rather than something much smaller...
But that finally makes sense. Silicon was supposed to be at it's limit at around 7nm, cause any smaller and You won't be able to properly separate gates from each other - electric charge would just jump through the "gap/wall". Yet we constantly hear about 4-5nm, like there's no problem at all. Now is proven: 5nm just in name, ~20nm in reality.
 

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You think this is bad? Lol. Welcome to TPU. Get used to it;)
Next time if you want corrections its a better idea to send the poster a PM or tag them in your reply with @

Post has been updated. Mistakes and errors happen, but we've always been open (as we should) to feedback and corrections. We too want to have quality content, but sometimes things fall through the cracks.
 
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But that finally makes sense. Silicon was supposed to be at it's limit at around 7nm, cause any smaller and You won't be able to properly separate gates from each other - electric charge would just jump through the "gap/wall". Yet we constantly hear about 4-5nm, like there's no problem at all. Now is proven: 5nm just in name, ~20nm in reality.
Using current manufacturing technology, yes. Although there's also that part where the electrons get too big and that's when we have a really big problem...
 
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If the difference in node pitch is so tiny, this just means that AMD's desktop designs are just this much better than Intel's desktop (power and performance per area), and that Intel is still ahead in laptops and possibly servers once IceLake-SP is released.

This has been known for a while, people still buy into the marketing ploy. On a daily basis I see people make fun of Intel for "still" being on 14nm. The "tech" community surrounding PCs likes to use a bunch of terms that they do not understand, which makes them easy fodder for the marketing and spin types.

Intel's main problem is not their node, never has been. It's sitting on the Skylake arch for too long. Going to Tiger Lake will change up the map on mobile, provided they can get quantity out.

I think Rocket Lake, despite being "14nm", will also be a significant part in terms of performance. It's basically a high frequency Tiger Lake without the Xe graphics. This article just reinforces that view.
 
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