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Samsung and TSMC Reportedly Struggling with 3 nm Yields

TheLostSwede

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According to Korean business news publication ChosunBiz, both Samsung and TSMC are struggling with their 3 nm node yields. The two companies have different approaches to their 3 nm nodes, with Samsung using GAA FET (Gate All Around), whereas TSMC is continuing with its FinFET technology. That said, TSMC has at least five known 3 nm nodes, of which two should be in production by now, assuming N3E has proved to be reliable enough to kick off. Samsung on the other hand has three known 3 nm nodes, with only one in production so far, called 3GAE.

ChosunBiz reports that neither company is getting the kind of yields that you'd expect from a node that should have been in volume production for around a year by now, with Samsung apparently being somewhat better than TSMC. At 60 and 50 percent respectively, neither Samsung nor TSMC are anywhere near decent yields. Anything below 70 percent is considered very poor and even the 60 percent claim in Samsungs case, is apparently limited to some kind of Chinese mining ASIC and doesn't include the SRAM you find in most modern processors. ChosunBiz also mentions a source familiar with Samsung's foundry business who mentions a yield closer to 50 percent for the company. The same source also mentions that Samsung needs to reach at least 70 percent yield to be able to attract major customers to its 3 nm node.



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Intel won't do any better. Now we know where the end of the smooth road is.
 
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Intel won't do any better. Now we know where the end of the smooth road is.

I doubt we will find out Intels yeilds
 
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I doubt we will find out Intels yeilds
If they are indeed going to offer manufacturing services, this information tends to emerge.

It also sounds strange to say that with a 60% yield Samsung would not attract customers, wasn't Qualcomm manufacturing the SD 8G1 in 4nm with yields of just 30%?
 
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bug

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Good. Chips were getting way too cheap, those yields will curb that trend :nutkick:
 
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Intel won't do any better. Now we know where the end of the smooth road is.
Intel 3 was said recently to be on track to be “manufacturing-ready” by the end of 2024.

There are Intel 3 test chips around, including a prototype UCIe chip for Synopsys that combines an Intel chiplet fabricated on Intel 3 with a TSMC chiplet fabricated on the N3E process node.
 

bug

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Intel 3 was said recently to be on track to be “manufacturing-ready” by the end of 2024.
End of 2024 is a year way. One would expect both TSMC's and Samsung's yields to pick up by then...
 
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If they are indeed going to offer manufacturing services, this information tends to emerge.

It also sounds strange to say that with a 60% yield Samsung would not attract consumers, wasn't Qualcomm manufacturing the SD 8G1 in 4nm with yields of just 30%?

I get the impression, and I could be wrong, that Samsung played ball for cheaper wafer prices or Qualcomm made a deal for KGD.

It would appear Samsung is unwilling to do that for 3nm, in which case Qualcomm demands 70% yield to buy whole wafers.

With SD8GEN3 appearing to be have both 4nm and 3nm versions from TSMC, it would appear Samsung has until Qualcomm starts general production of their next chip to get yields up.

I would argue that's the important goal post, as I think over time Nuvia's Oryon is going to be a big deal considering it's performance and likely proliferation. It might actually start the ARM revolution in PCs.

That would be a big get. I wonder if they'll talk about their choice of fab and/or production timelines at Snapdragon Summit (24-26th of this month). It's possible they might, but I don't know.

The current word is they *may* dual-source 3nm from TSMC and Samsung, but I'm sure they'd love to use Samsung exclusively if they can get yields up enough for it to make financial sense versus TSMC.
 
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If they are indeed going to offer manufacturing services, this information tends to emerge.

It also sounds strange to say that with a 60% yield Samsung would not attract consumers, wasn't Qualcomm manufacturing the SD 8G1 in 4nm with yields of just 30%?
"Major customers", not "consumers". Those would be businesses they are referring to
 
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Intel 3 was said recently to be on track to be “manufacturing-ready” by the end of 2024.

There are Intel 3 test chips around, including a prototype UCIe chip for Synopsys that combines an Intel chiplet fabricated on Intel 3 with a TSMC chiplet fabricated on the N3E process node.
Doubt it, rumours are AMD is skipping 3nm for the next gen entirely as well. Find it hard to believe of all companies, Intel, the only company still using 10 nm chips, who makes the most inefficient cpu's in the world and has no modern experience shrinking chips, are going to be the ones to innovate on 3nm while everyone else failed.
 
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All to keep prices high on their existing nodes
 
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Intel 3 was said recently to be on track to be “manufacturing-ready” by the end of 2024.

There are Intel 3 test chips around, including a prototype UCIe chip for Synopsys that combines an Intel chiplet fabricated on Intel 3 with a TSMC chiplet fabricated on the N3E process node.
I'd vary about whatever Intel says. Remember they were like 3 years late with 10nm and then 2 more years before they could produce anything above a 25W TDP on it, and everyone online was laughing at their 14nm++++++ node cpu refreshes.
 
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Doubt it, rumours are AMD is skipping 3nm for the next gen entirely as well. Find it hard to believe of all companies, Intel, the only company still using 10 nm chips, who makes the most inefficient cpu's in the world and has no modern experience shrinking chips, are going to be the ones to innovate on 3nm while everyone else failed.
Intel 3 isn't "3nm", Just like the soon to be released MTL Intel 4 are not "4nm". It's an optimized "7nm" that going to be comparable to TSMC 3nm. The current Intel 10nm is called intel 7 because it's equivalent to TSMC 7nm.
Nodes names are a marketing name everywhere, ever since fabs engineers figured out that at some point simply making things smaller would bring a bunch of issues. TSMC 3nm isn't actually 3nm, but is as performant as a real 3nm would be in theory. Intel choose to use a "TSMC rating system" to avoid people thinking that their nodes are inferior because the number is bigger.
 
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Intel 3 was said recently to be on track to be “manufacturing-ready” by the end of 2024.

There are Intel 3 test chips around, including a prototype UCIe chip for Synopsys that combines an Intel chiplet fabricated on Intel 3 with a TSMC chiplet fabricated on the N3E process node.
Doubt it, rumours are AMD is skipping 3nm for the next gen entirely as well. Find it hard to believe of all companies, Intel, the only company still using 10 nm chips, who makes the most inefficient cpu's in the world and has no modern experience shrinking chips, are going to be the ones to innovate on 3nm while everyone else failed.
I'd vary about whatever Intel says. Remember they were like 3 years late with 10nm and then 2 more years before they could produce anything above a 25W TDP on it, and everyone online was laughing at their 14nm++++++ node cpu refreshes.
Exactly. You mean to tell me that a company who has yet to release their first 7nm chips (whatever they call it in marketing) will be able to somehow leapfrog the competition a year from now?

And IF Intel does start producing 3nm at the end of 2024 then they are still a year behind. TSMC and Samsung are producing 3nm now, regardless of the yields.
Also it's a pretty big IF that Intel's yields will be above 70% from the get go considering the fact that their 7nm was delayed more than half a year and they are still unable to produce 8+32 desktop dies on it. Hence why Meteor Lake will be limited to laptops and NUC's and why they needed Raptor Lake Refresh on 10nm.
Intel 3 isn't "3nm", Just like the soon to be released MTL Intel 4 are not "4nm". It's an optimized "7nm" that going to be comparable to TSMC 3nm. The current Intel 10nm is called intel 7 because it's equivalent to TSMC 7nm.
Yeah that is what Intel says but we can all look at benchmarks and see that their 10nm that they call 7nm TSMC equivalent is not on par with it considering that it consumes more power. It's still 10nm.
Nodes names are a marketing name everywhere, ever since fabs engineers figured out that at some point simply making things smaller would bring a bunch of issues. TSMC 3nm isn't actually 3nm, but is as performant as a real 3nm would be in theory.
Of course it's not. It's more like 20-40nm.
Intel choose to use a "TSMC rating system" to avoid people thinking that their nodes are inferior because the number is bigger.
Intel chose to use way more dubious rating system that TSMC uses. Coupled with constant delays and cancellations it's the reason why people dont trust Intel.
 
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So again, what is this 3nm means?? What measures 3nm ?
Why do those companies are not getting properly regulated and fined for false advertisement??
 
D

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Great high prices :banghead: I was listening to an nVidia representative, blaming node prices for doubling the price for 4080 forgetting that the 4080 has a tiny die they basically tripled the price.
I'd vary about whatever Intel says. Remember they were like 3 years late with 10nm and then 2 more years before they could produce anything above a 25W TDP on it, and everyone online was laughing at their 14nm++++++ node cpu refreshes.
Forgot what happened to Intel back then, they were way ahead of everyone then got stuck with 14nm.
 

hs4

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1) Comparing the number of fins and library height of standard cells for each company's nodes, which are the true physical length, Intel 4's high-performance cell (3/3 fins) is smaller than that of N5/N4 (3/3 fins) and about halfway between that of N3's HP cell (3/2 fins). Intel 4, once called 7nm, is about 1.5 generations ahead of TSMC's 7nm. It is now common knowledge that the notation 'X nm' is just a brand and does not mean physical length. If someone claims that, it means that they do not understand the number of fins or DTCO.

Screenshot 2023-10-06 at 13-54-59 Correctly Understanding the Intel 4 Scaling Value TechInsights.png

Figure from Techinsight


2) Intel 7 can consume a large amount of power simply because it has a higher maximum clock. If Raptor lake is clock-limited to the same clock/same benchmark score as the Ryzen 5000 series (N7), it will consume less power than the subject of comparison.
The Ryzen 7000 series (N5) is not much different in power efficiency from Raptor lake as a result of increasing the maximum clock, and the 7800X3D is more efficient due to lower clock due to lack of heat dissipation capability by the V-Cache.
スクリーンショット 2023-10-06 151945.png


3) Intel 4 has already achieved higher yields than Intel 10nm in the Tiger lake era, and Intel 3 is expected to have useful yields as it will be manufactured on the same equipment as Intel 4 with only minor changes in processing steps. Sierra Forest, will be available in the 1H 2024, uses a 600 mm² class die. It means that Intel 3 has the yield to make it profitable with such a large die.
Intel 3/4 was originally scheduled to start in the Raptor lake year, and the main delay is believed to have been caused by COVID's delay in delivering the manufacturing equipment, during which time the nodes matured to yield at the second year of operation level.

Screenshot 2023-10-06 at 13-53-21 Intel Meteor Lake Technical Deep Dive.png
 
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1) Comparing the number of fins and library height of standard cells for each company's nodes, which are the true physical length, Intel 4's high-performance cell (3/3 fins) is smaller than that of N5/N4 (3/3 fins) and about halfway between that of N3's HP cell (3/2 fins). Intel 4, once called 7nm, is about 1.5 generations ahead of TSMC's 7nm. It is now common knowledge that the notation 'X nm' is just a brand and does not mean physical length. If someone claims that, it means that they do not understand the number of fins or DTCO.
Intel 4 problem isn't yield but cost. Reason for that is that they paid a lot money at ASML for equipment and R&D. They are only making compute tiles at this moment in this node which are about 40 - 60mm² (U/H). So yields are acceptable because tiny chips (tiles) lets see how it works with larger area.
 
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