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Intel "Sapphire Rapids" Brings PCIe Gen 5 and DDR5 to the Data-Center

As if the mother of all ironies, prior to its effective death-sentence dealt by the U.S. Department of Commerce, Huawei's server business developed an ambitious product roadmap for its Fusion Server family, aligning with Intel's enterprise processor roadmap. It describes in great detail the key features of these processors, such as core-counts, platform, and I/O. The "Sapphire Rapids" processor will introduce the biggest I/O advancements in close to a decade, when it releases sometime in 2021.

With an unannounced CPU core-count, the "Sapphire Rapids-SP" processor will introduce DDR5 memory support to the data-center, which aims to double bandwidth and memory capacity over the DDR4 generation. The processor features an 8-channel (512-bit wide) DDR5 memory interface. The second major I/O introduction is PCI-Express gen 5.0, which not only doubles bandwidth over gen 4.0 to 32 Gbps per lane, but also comes with a constellation of data-center-relevant features that Intel is pushing out in advance as part of the CXL Interconnect. CXL and PCIe gen 5 are practically identical.

AMD 3rd Generation Ryzen Probable SKUs, Specs, Pricing Leaked?

One of our readers tipped us off with a very plausible looking image that drops a motherlode of information about what AMD's 2nd generation Ryzen (aka Ryzen 3000 series) processor lineup could look like. This includes a vast selection of SKUs, their CPU and iGPU core configurations, clock-speeds, and OEM channel pricing. The list speaks of a reentry for 7th generation A-series "Excavator" as Duron X4 series, followed by Duron 300GE-series based on a highly cut down "Raven Ridge," Athlon 300GE 2-core/4-thread based on an implausible "Zen+ 12 nm" APU die, followed by quad-core Ryzen 3 3000 series processors with and without iGPUs, making up the company's entry-level product lineup.

The core counts seem to jump from 4-core straight to 8-core, with no 6-core in between, for the Ryzen 5 series. This is also where AMD's new IP, the 7 nm "Zen 2" architecture, begins. There appears to be a large APU die (or a 3-chip MCM) with an 8-core CPU and 20-CU iGPU, which makes up certain Ryzen 5 SKUs. These chips are either 8-core/8-thread or 8-core/16-thread. The Ryzen 7 series is made up of 12-core/24-thread processors that are devoid of iGPU. The new Ryzen 9 series extension caps off the lineup with 16-core/32-thread SKUs. And these are just socket AM4.

AMD Zen 2 "Rome" MCM Pictured Up Close

Here is the clearest picture of AMD "Rome," codename for the company's next-generation EPYC socket SP3r2 processor, which is a multi-chip module of 9 chiplets (up from four). While first-generation EPYC MCMs (and Ryzen Threadripper) were essentially "4P-on-a-stick," the new "Rome" MCM takes the concept further, by introducing a new centralized uncore component called the I/O die. Up to eight 7 nm "Zen 2" CPU dies surround this large 14 nm die, and connect to it via substrate, using InfinityFabric, without needing a silicon interposer. Each CPU chiplet features 8 cores, and hence we have 64 cores in total.

The CPU dies themselves are significantly smaller than current-generation "Zeppelin" dies, although looking at their size, we're not sure if they're packing disabled integrated memory controllers or PCIe roots anymore. While the transition to 7 nm can be expected to significantly reduce die size, groups of two dies appear to be making up the die-area of a single "Zeppelin." It's possible that the CPU chiplets in "Rome" physically lack an integrated northbridge and southbridge, and only feature a broad InfinityFabric interface. The I/O die handles memory, PCIe, and southbridge functions, featuring an 8-channel DDR4 memory interface that's as monolithic as Intel's implementations, a PCI-Express gen 4.0 root-complex, and other I/O.

Intel's Ice Lake Xeon Processor Details Leaked: LGA 4189, 8-Channel Memory

The Power Stamp Alliance (PSA) has posted some details on Intel's upcoming high-performance, 10 nm architecture. Code-named Ice Lake, the Xeon parts of this design will apparently usher in yet another new socket (socket LGA 4189, compared to the socket LGA 3647 solution for Kaby lake and upcoming Cascade Lake designs). TDP is being shown as increased with Intel's Ice Lake designs, with an "up to" 230 W TDp - more than the Skylake or Cascade Lake-based platforms, which just screams at higher core counts (and other features such as OmniPath or on-package FPGAs).

Digging a little deeper into the documentation released by the PSA shows Intel's Ice Lake natively supporting 8-channel memory as well, which makes sense, considering the growing needs in both available memory capacity, and actual throughput, that just keeps rising. More than an interesting, unexpected development, it's a sign of the times.
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