Photos from Qualcomm's Snapdragon Summit in Hawaii, courtesy of ComputerBase, confirm the company is pushing advanced packaging format as hard as silicon this generation: the top-tier X2E-96-100 was shown with LPDDR5X memory arrays stacked on-package around an 18-core Oryon 3 cluster. This layout is designed to reduce latency and increase sustained throughput for demanding AI and media workloads. Qualcomm appears to be offering three distinct X2 configurations to balance performance, memory bandwidth, and power: a SiP (system-in-package) Extreme with very wide memory channels for peak sustained bandwidth, plus two off-package variants that rely on narrower channels but still aim for high single-thread and burst performance.

The pictured Extreme SKU, X2E-96-100, is an 18-core part with a minimum of 48 GB and a maximum of 128 GB+ of on-package LPDDR5X memory in a 12-channel configuration, delivering 228 GB/s bandwidth. It features a CPU top clock of around 4.6 GHz with a two-core boost to 5.0 GHz, and a peak GPU clock of near 1.85 GHz. The X2E-88-100 retains the 18 cores but utilizes off-package memory on an 8-channel bus at 152 GB/s, featuring base clocks of nearly 4.0 GHz and a 2-core turbo boost up to 4.7 GHz. The more compact X2E-80-100 drops to 12 cores, also featuring off-package 8-channel memory with a bandwidth of around 152 GB/s, a 4.0 GHz baseline, and single-core and dual-core bursts of up to 4.7 GHz and 4.4 GHz, respectively. The chip is built on a 3 nm node from TSMC and offers up to a dozen PCIe Gen 5 lanes, dual PCIe 5.0 lanes for NVMe, USB4, and 3× USB-C, as well as Wi-Fi 7 and Bluetooth 5.4 connectivity. It uses a Spectra ISP and an Adreno VPU capable of multi-8K encode/decode and simultaneous 8K workflows.