To meet the growing demand for AI infrastructure, AMD (NASDAQ: AMD) today announced more than $10 billion in investments across the Taiwan ecosystem to expand strategic partnerships and scale advanced packaging manufacturing for next-generation AI infrastructure. Working with strategic partners in Taiwan and globally, AMD is advancing leading-edge silicon, packaging and manufacturing technologies that enable higher performance, greater efficiency and faster deployment of AI systems. These efforts build on AMD's deep ecosystem partnerships and long-standing leadership in chiplet architectures, high-bandwidth memory integration, 3D hybrid bonding and rack-scale system design for next-generation AI infrastructure.

"As AI adoption accelerates, our global customers are rapidly scaling AI infrastructure to meet growing compute demand," said Dr. Lisa Su, Chair and CEO, AMD. "By combining AMD leadership in high-performance computing with the Taiwan ecosystem and our strategic global partners, we are enabling integrated, rack-scale AI infrastructure that helps customers accelerate deployment of next-generation AI systems."

While AMD hasn't launched its upcoming Instinct MI400 series of accelerators yet, the company has started preparing its supply chain for what comes after. Thanks to SemiAnalysis, we have a clearer picture of what AMD's Instinct MI500 UAL256 rack will look like. At the base of each compute node, there will be a single "Verano" CPU paired with four Instinct MI500 accelerators. With up to 64 nodes, split across two 32-node racks, AMD plans to enable 256 logical GPUs and 64 CPUs per mega pod, working in tandem for advanced AI and HPC workloads. Instinct MI500s UAL256 will be AMD's second-generation rack-scale system, following the upcoming Instinct MI450X IF128 aka "Helios", scheduled for the second half of 2026. The Instinct MI500 UAL256 scale-up mega pod is scheduled to arrive in 2027, just in time for Verano and Instinct MI500 accelerator.

The Instinct MI500 UAL256 scale-up mega pod splits the compute into two 32-rack cabinets, with a single central rack connecting them and hosting 18 switching trays for networking. Each of these networking trays contains four 102.4T "Vulcano" switch ASICs, designed for 800G external throughput, and manufactured on TSMC's 3 nm node. For the central processor, AMD showed few details at its Advancing AI event, which claimed that Verano introduces the "Zen 7" microarchitecture for even higher IPC and support for even newer instruction sets. For now, it's not clear if AMD will increase CPU core counts beyond the up to 256 cores per package of "Venice." Still, we're hearing that Verano will retain the Socket SP7 infrastructure, which means it will likely retain the memory and PCIe interfaces introduced in 2026, such as PCIe Gen 6, UALink, and Ultra Ethernet.

At its "Advancing AI 2025" event, AMD rolled out its new Instinct MI350 lineup on the CDNA 4 architecture and teased the upcoming UDNA-based AI accelerator. True to its roughly one-year refresh rhythm, the company confirmed that the Instinct MI400 series will land in early 2026, showcasing a huge leap in memory, interconnect bandwidth, and raw compute power. Each MI400 card features twelve HBM4 stacks, providing a whopping 432 GB of on-package memory and pushing nearly 19.6 TB/s of memory bandwidth. Those early HBM4 modules deliver approximately 1.6 TB/s each, just shy of the 2 TB/s mark. On the compute front, AMD pegs the MI400 at 20 PetaFLOPS of FP8 throughput and 40 PetaFLOPS of FP4, doubling the sparse-matrix performance of today's MI355X cards. But the real game-changer is how AMD is scaling those GPUs. Until now, you could connect up to eight cards via Infinity Fabric, and anything beyond that had to go over Ethernet.

The MI400's upgraded fabric link now offers 300 GB/s, nearly twice the speed of the MI350 series, allowing you to build full-rack clusters without relying on slower networks. That upgrade paves the way for "Helios," AMD's fully integrated AI rack solution. It combines upcoming EPYC "Venice" CPUs with MI400 GPUs and trim-to-fit networking gear, offering a turnkey setup for data center operators. AMD didn't shy away from comparisons, either. A Helios rack with 72 MI400 cards delivers approximately 3.1 ExaFLOPS of tensor performance and 31 TB of HBM4 memory. NVIDIA's Vera Rubin system, slated to feature 72 GPUs and 288 GB of memory each, is expected to achieve around 3.6 ExaFLOPS, with AMD's capabilities surpassing it in both bandwidth and capacity. And if that's not enough, whispers of a beefed-up MI450X IF128 system are already swirling. Due in late 2026, it would directly link 128 GPUs with Infinity Fabric at 1.8 TB/s bidirectional per device, unlocking truly massive rack-scale AI clusters.

According to SemiAnalysis, AMD has planned its first-ever rack-scale GPU cluster for the second half of 2026, when it shows its first rack-scale accelerator, the Instinct MI450X IF128. Built on what's expected to be a 3 nm-class TSMC process and packaged with CoWoS-L, each MI450X IF128 card will include at least 288 GB of HBM4 memory. That memory will sustain up to 18 TB/s of bandwidth, driving around 50 PetaFLOPS of FP4 compute while drawing between 1.6 and 2.0 kW of power. In our recent article, we outlined that AMD split the Instinct MI400 series into HPC-first MI430X and MI450X for AI. Now for AI-focused MI450X, the company created both an "IF64" backplane for simpler single-rack installs and the full-blown "IF128" for maximum density. The IF128 version links 128 GPUs over an Ethernet-based Infinity Fabric network and uses UALink instead of PCIe to connect each GPU to three built-in Pensando 800 GbE NICs. That design delivers about 1.8 TB/s of unidirectional bandwidth per GPU and a total of 2,304 TB/s across the rack.

With 128 GPUs each offering 50 PetaFLOPS of FP4 compute and 288 GB of HBM4 memory, the MI450X IF128 system delivers a combined 6,400 PetaFLOPS and 36.9 TB of high-bandwidth memory, and MI450X IF64 provides about half of that. Since AI deployments require massive density of rack systems, AMD plans to possibly outnumber NVIDIA's upcoming system known as "Vera Rubin" VR200 NVL144 (144 compute dies, 72 GPUs), which tops out at 3,600 PetaFLOPS and 936 TB/s of memory bandwidth—about half of what AMD's IF128 approach promises. AMD will have a possibly more powerful system architecture than NVIDIA until the launch of VR300 "Ultra" NVL576, which has 144 GPUs, each carrying four compute dies, totaling 576 compute chiplets.

AMD is gearing up to expand its Instinct MI family in the latter half of 2026 with two purpose-built UDNA-based accelerators. These new models, MI430X UL4 and MI450X, will cater respectively to high-precision HPC tasks and large-scale AI workloads. The MI430X UL4 is designed for applications that rely heavily on double-precision FP64 floating-point performance, such as scientific simulations, climate modeling, and others. It features a large array of FP64 tensor cores, ensuring consistent throughput for tightly coupled compute jobs. Because a dedicated UALink switch from partners like Astera Labs or Broadcom won't be available at launch, AMD has chosen a four-GPU point-to-point mesh configuration for the MI430X UL4. This limited scale-up approach keeps latency low and synchronization tight, making it ideal for small cluster deployments. On the AI side, the MI450X embraces Ethernet-based Ultra Ethernet for scale-out.

With UEC-ready switches already on the market, this open-standard networking solution lets users build expansive AI farms across dozens or even hundreds of nodes. By relying on established Ethernet technology instead of the new UALink ecosystem, AMD provides customers with immediate, hardware-accelerated networking for both inference and training. While UALink promises an open, vendor-neutral accelerator-to-accelerator fabric, its progress has been slow. Committee reviews and limited investment in switch silicon have delayed switch availability. Broadcom, viewed as the primary UALink switch supplier, has been cautious about its commitment, given expected lower volumes compared to Ethernet alternatives. AMD's acceleration segmentation addresses these realities. The MI430X UL4 delivers high-precision compute in compact GPU meshes. The MI450X offers large-scale AI connectivity via Ethernet. Should UALink switch development catch up in the future, AMD could revisit native GPU-to-GPU fabrics.