AMD is planning a significant return to establishing new manufacturing ties with its former silicon manufacturing venture, which it sold back in 2008. According to recent reports, AMD intends to collaborate with GlobalFoundries for new Co-Packaged Optics (CPO) for the next-generation Instinct MI500 series of AI accelerators. CPO technology will help AMD remain competitive in the AI data center space, where signal transfer is limited by traditional copper-based wiring. By harnessing the power and speed of light, CPO technology will enable data transfer between multiple nodes, and even multiple facilities, without the speed loss and increased latency associated with copper-based connections. Consequently, AMD is investing considerable effort to secure Photonics Integrated Circuit (PIC) manufacturing with its former partner, GlobalFoundries, which will handle PIC manufacturing, while the actual packaging will be managed by ASE to finalize the CPO design. This approach allows AMD to leverage the strengths of both companies, likely resulting in the best solution for its systems next year.

The Instinct MI500 series of AI accelerators is scheduled for release in 2027, as this year's lineup focuses on the Instinct MI400 series, which includes multiple SKUs for AI and HPC workloads. While these designs are already among the industry's leading AI accelerators, AMD aims to enhance performance further with the 2027 release using CPO technology. This will significantly contribute to delivering a solution that uses less power and offers much higher overall bandwidth compared to traditional copper data transfers. However, AMD is not alone in this CPO push. NVIDIA is also collaborating with semiconductor makers to develop a CPO system for "Vera Rubin," particularly the "Rubin Ultra" variant.

At its Financial Analyst Day 2025, AMD shared new details about its upcoming Instinct MI400 and MI500 AI accelerators. The Instinct MI400 series set to launch in 2026, will be based on the new CDNA 5 architecture. AMD claims it will deliver up to 40 FP4 and 20 FP8 PFLOPs, roughly twice the compute performance of the current MI350. The GPUs also move to HBM4 memory from HMB3e, increasing capacity from 288 GB to 432 GB and raising total bandwidth from 8 TB/s to 19.6 TB/s. Each GPU provides 300 GB/s of scale-out bandwidth and adds broader AI data format support along with expanded AI pipelines. Two models are planned: the Instinct MI455X for large-scale AI training and inference, and the MI430X for HPC and sovereign AI. The MI430X features FP64 hardware based support and hybrid CPU+GPU compute capability, while retaining the same HBM4 memory subsystem as the MI455X. The MI400 series also moves away from the CoWoS-S to the CoWoS-L (Local Silicon Interconnect) advanced packaging technology.

AMD compares the MI400 lineup to NVIDIA's upcoming Vera Rubin series, claiming similar compute performance and memory bandwidth, but 1.5× higher memory capacity and scale-out bandwidth. During her presentation, Dr. Lisa Su said that AMD's Instinct MI400 accelerators will be available to clients and partners from day one, while the next-generation MI500 is already in advanced design stages. AMD is also now moving to an annual refresh cycle for its Instinct products, confirming that its next-gen MI500 series will be launched in 2027.

While AMD hasn't launched its upcoming Instinct MI400 series of accelerators yet, the company has started preparing its supply chain for what comes after. Thanks to SemiAnalysis, we have a clearer picture of what AMD's Instinct MI500 UAL256 rack will look like. At the base of each compute node, there will be a single "Verano" CPU paired with four Instinct MI500 accelerators. With up to 64 nodes, split across two 32-node racks, AMD plans to enable 256 logical GPUs and 64 CPUs per mega pod, working in tandem for advanced AI and HPC workloads. Instinct MI500s UAL256 will be AMD's second-generation rack-scale system, following the upcoming Instinct MI450X IF128 aka "Helios", scheduled for the second half of 2026. The Instinct MI500 UAL256 scale-up mega pod is scheduled to arrive in 2027, just in time for Verano and Instinct MI500 accelerator.

The Instinct MI500 UAL256 scale-up mega pod splits the compute into two 32-rack cabinets, with a single central rack connecting them and hosting 18 switching trays for networking. Each of these networking trays contains four 102.4T "Vulcano" switch ASICs, designed for 800G external throughput, and manufactured on TSMC's 3 nm node. For the central processor, AMD showed few details at its Advancing AI event, which claimed that Verano introduces the "Zen 7" microarchitecture for even higher IPC and support for even newer instruction sets. For now, it's not clear if AMD will increase CPU core counts beyond the up to 256 cores per package of "Venice." Still, we're hearing that Verano will retain the Socket SP7 infrastructure, which means it will likely retain the memory and PCIe interfaces introduced in 2026, such as PCIe Gen 6, UALink, and Ultra Ethernet.