Socionext Inc., a global leader in System-on-Chip (SoC) design and advanced semiconductor solutions, introduces "Flexlets", a new class of configurable chiplets designed to advance heterogenous integration. As traditional monolithic SoC designs face physical and economic limits—reticle size constraints, yield challenges, and thermal bottlenecks- the industry is turning toward chiplet-based design, where designers can integrate their core features and interface functionalities, provided as chiplets, into a packaged device to improve performance, cost, and accelerate time-to-market.

While chiplet technology opens exciting possibilities for modular designs and scalability, many current solutions are derived from fixed-function ASSPs, limiting flexibility and customization. Socionext's Flexlets overcome this by offering a configurable library of chiplet designs at the RTL level. Unlike traditional approaches, Flexlets empower customers to tailor performance to their unique application needs - whether in high-performance computing, advanced networking, or next-generation automotive systems.

Marvell Technology, Inc. (NASDAQ: MRVL), a leader in data infrastructure semiconductor solutions, today announced the industry's first 2 nm 64 Gbps bi-directional die-to-die (D2D) interconnect, enabling chip designers to significantly boost the bandwidth and performance of next-generation XPUs while reducing power and silicon area. Delivering 32 Gbps of simultaneous two-way connectivity over a single wire, the interface IP—also available in 3 nm—sets a new standard for performance, power efficiency, and resiliency to meet the scaling demands of next-generation data centers.

The Marvell 64 Gbps bi-directional D2D interface offers bandwidth density over 30 Tbps/mm, more than three times the bandwidth density of UCIe at equivalent speeds, and a minimal depth configuration that reduces compute die area requirements to 15% compared to conventional implementations. The interface IP is also the industry's first in its class to feature advanced adaptive power management that automatically adjusts device activity to bursty data center traffic. This innovation reduces interface power consumption by up to 75% with normal workloads and up to 42% during peak traffic periods.

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions expanded its custom technology platform with the launch of the industry's first 2 nm custom Static Random Access Memory (SRAM), designed to boost the performance of custom XPUs and devices powering cloud data centers and AI clusters. Combining advanced custom circuitry and software from Marvell with core SRAM and cutting-edge 2 nm process technology, Marvell custom SRAM delivers up to 6 gigabits of high-speed memory while significantly reducing memory power consumption and die area at comparable densities.

Custom SRAM is the latest Marvell innovation designed to enhance memory hierarchy performance within accelerated infrastructure. Marvell previously introduced its CXL technology for integration into custom silicon to add terabytes of memory and supplemental compute capacity to cloud servers and unveiled custom HBM technology that increases memory capacity by up to 33% while reducing the space and power required for dense high-bandwidth memory (HBM) stacks inside XPUs.

More confirmations regarding the final release of the Intel Arc "Battlemage" B770 GPU have landed, this time with the update of the popular AIDA64 tool. Just days after support for BMG-G31 GPUs, supposedly the SKUs behind the higher-end B770 and B750 models, has landed in the open-source Mesa driver, diagnostic tools are next. In the latest AIDA64 beta version 7.99.7817, FinalWire has added an interesting "GPU information for Intel Battlemage (BMG-G31)" section as a feature update. This means that the tool can now officially recognize Intel's upcoming GPUs and allow users to perform diagnostics. Additionally, the tool also supports the now finalized PCI Express 7.0 controllers and devices, as PCI-SIG has ratified the final specifications of the PCIe Gen 7 standard.

With this confirmation, higher-end Intel Arc B770 and B750 GPUs are getting more credibility for an actual release. We expect to hear more about it in the coming weeks as the rumored Q4 launch nears. Earlier rumors suggest that Intel will pair 32 Xe2 cores for the B770 model with 16 GB of GDDR6 memory on a 256-bit bus. Will Intel satisfy the needs of Arc graphics gamers who have been waiting for a higher-end card remains to be seen. Drop your expectations in the comments, and let us know.

PCI-SIG, the consortium that governs the PCI Express I/O interconnect, released draft specification version 0.7 for the upcoming PCI-Express 7.0 standard (or PCIe Gen 7). An early-2025 release of this draft could indicate that PCIe Gen 7 gets finalized into specification version 1.0 by the end of 2025, from where implementers can pick it up to design their devices around. We are now at 32 Gbps per lane per direction with PCIe Gen 5, and PCIe Gen 6 doubles it to 64 Gbps, which would mean PCIe Gen 7 will double that further to 128 Gbps per lane per direction. PCI-Express 7.0 x1 would offer the same bandwidth as PCI-Express 3.0 x16. We could realistically expect the first computing platforms implementing PCIe Gen 7 to come out around 2027 or even 2028. PCIe forms the physical layer for a number of derivative standards, such as CXL, Thunderbolt, USB (USB 3.0 onwards), NVMe, SDexpress, CFexpress, and DMI.Many Thanks to Tumble George for the tip

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, demonstrates its industry-leading 3 nm PCIe Gen 7 connectivity at the OCP Global Summit, October 15-17, at the San Jose Convention Center. PCIe Gen 7 doubles data transfer speeds, enabling continued scaling of compute fabrics inside accelerated server platforms, general-purpose servers, CXL systems and disaggregated infrastructure. Building on its widely deployed PAM4 technology and utilizing its industry-leading accelerated infrastructure silicon platform, Marvell has developed the industry's most comprehensive interconnect portfolio addressing all high-bandwidth optical and copper connections in AI data centers. This innovative portfolio empowers cloud data center operators to optimize their infrastructure for their specific architectures and workloads to meet the exponential demands of AI.

Marvell pioneered PAM4 technology over a decade ago and leads the industry in PAM4 interconnect shipments. Today, most of the optical interconnects used in data center backend and frontend networks are based on PAM4 technology. As compared to PCIe Gen 5, which was based on NRZ modulation, PCIe Gen 6 and 7 require the use of PAM4 modulation. With its recent PCIe Gen 6 retimer announcement and this PCIe Gen 7 demonstration, Marvell extends its industry-leading PAM4-based optical and copper interconnect portfolio beyond Ethernet and InfiniBand into copper and optical PCIe, CXL and proprietary compute fabric links.