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Intel's next-generation Pentium Silver "Snow Ridge" SoC, featuring "Tremont" CPU cores, could see the debut of an L3 cache to the segment. Intel CPU cores in this segment, such as the "Goldmont Plus," only feature shared L2 caches across 4-core modules. The introduction of L3 cache was indicated by a new performance counter "MEM_LOAD_UOPS_RETIRED_L3_HIT," with a description clearly mentioning a "level 3 cache." The introduction of L3 cache as the SoC's LLC (last level cache) could mean Intel is trying to improve inter-component communication by introducting the L3 cache as "town-square" for the various components of the SoC, such as the CPU cores, the iGPU, and the integrated chipset. The company could deploy a ring-bus interconnect that has ring-stops at the various components, and slices of this L3 cache. Intel is building the "Snow Ridge" silicon on its swanky new 10 nm silicon fabrication process, and the chip could see a 2020 debut targeting network infrastructure devices.