THX, Ltd., a world-class high-fidelity audio and video tuning, certification, and technology company, and producer of the iconic THX Deep Note Trailers, has announced today the expansion of its THX Spatial Audio technology. Innovating for enjoyment of gaming, movies and music while listening on consumer electronics and mobile devices such as laptops, headphones, earbuds and soundbars, THX today announced a feature-rich new immersive audio architecture, THX Spatial Audio+.

To ensure that gamers and audio- and videophiles alike can enjoy the pinpoint audio accuracy and true-to-life realism of immersive entertainment like never before comes THX Spatial Audio+. THX Spatial Audio+ improves the core spatial experience with an enhanced and flexible architecture designed to support continued innovation, including such unique features as adding height channels to the immersion and camera-based AI head tracking, depending upon the demands of the device.

Audioscenic, the UK-based audio technology innovator, announces a technology collaboration with Philips and semiconductor solutions leader NXP Semiconductors, to demonstrate the world's first reference design for gaming soundbars. This breakthrough combines Audioscenic Amphi Hi-D spatial audio featuring AI position sensing with Acoustic Echo Cancellation (AEC) from Philips BeClear. Powered by the NXP i.MX 8M Mini applications processor, this technology enables soundbar manufacturers to deliver fully immersive, location-accurate game audio simultaneously with crystal-clear voice chat—a combination previously unachievable in gaming soundbars. Product designers, product managers, and engineers can experience the reference design in person at Computex Taipei 2025.

Gamers have long faced a trade-off: enjoy rich, immersive sound through speakers or have clear voice communication with teammates through headsets. While headsets have dominated hardcore gaming, many players prefer speaker systems like soundbars for extended comfort without headset fatigue, and a more natural "room-filling" audio experience versus the inside-your-head sound of headsets.

Infineon Technologies AG is revolutionizing the power delivery architecture required for future AI data centers. In collaboration with NVIDIA, Infineon is developing the next generation of power systems based on a new architecture with central power generation of 800 V high-voltage direct current (HVDC). The new system architecture significantly increases energy-efficient power distribution across the data center and allows power conversion directly at the AI chip (Graphic Processing Unit, GPU) within the server board. Infineon's expertise in power conversion solutions from grid to core based on all relevant semiconductor materials silicon (Si), silicon carbide (SiC) and gallium nitride (GaN) is accelerating the roadmap to a full scale HVDC architecture.

This revolutionary step paves the way for the implementation of advanced power delivery architectures in accelerated computing data centers and will further enhance reliability and efficiency. As AI data centers already are going beyond 100,000 individual GPUs, the need for more efficient power delivery is becoming increasingly important. AI data centers will require power outputs of one megawatt (MW) and more per IT rack before the end of the decade. Therefore, the HVDC architecture coupled with high-density multiphase solutions will set a new standard for the industry, driving the development of high-quality components and power distribution systems.

Samsung Display is participating in COMPUTEX TAIPEI 2025, Asia's largest IT trade show, for the first time, showcasing its cutting-edge OLED display technologies. The company announced today that it will exhibit at COMPUTEX TAIPEI 2025, taking place May 20 to 23 at the Taipei Nangang Exhibition Center Hall 2, it will host a private exhibition for clients, unveiling its latest IT OLED portfolio for applications like laptops, tablets, monitors and other IT devices.

Samsung Display is set to unveil UT One for the first time alongside a range of low-power solutions optimized for IT devices such as laptops and tablets. The company will also showcase QD-OLED prototypes along with an ultra-high resolution and ultra-high refresh rate that will change the premium monitor market. In addition, wheeled dual-arm robots Rainbow Robotics, a company that specializes in robotic platforms, will perform a welcome show to demonstrate the slimness and light weight characteristics of Samsung OLED, set to leave a lasting impression on clients visiting our booth.

Driven by advancements in cryptographic research and the need for stronger security measures, the National Security Agency (NSA) introduced the Commercial National Security Algorithm Suite 2.0 (CNSA 2.0) to establish a set of quantum-resistant cryptographic standards. The NSA is now urging data center and computing markets to become post-quantum ready within the next two years. To help system architects meet evolving security demands, Microchip Technology has developed its MEC175xB embedded controllers with embedded immutable post-quantum cryptography support.

As a standalone controller, the MEC175xB family employs a modular approach for developers to efficiently adopt post-quantum cryptography, helping ensure long-term data protection without compromising existing functionality. These low-power controllers are designed with National Institute of Standards and Technology (NIST) approved post-quantum cryptographic algorithms, configurable secure boot solutions and an advanced Enhanced Serial Peripheral Interface (eSPI).

Samsung Display announced on May 13 that it will take part in Display Week 2025, held from May 13 to 15 at the McEnery Convention Center in San Jose, California. The event, hosted by the Society for Information Display (SID), brings together display companies and experts from around the world to share cutting-edge technologies and R&D achievements.

Samsung Display is set to unveil a range of next-generation display technologies, including the industry's first non-cadmium 400-nit EL-QD and a 5,000 pixels-per-inch (PPI) RGB OLED on Silicon (OLEDoS) at Display Week 2025, reinforcing its leadership in cutting-edge panel technology. The company will also highlight its leadership in OLED innovation through a range of future-oriented technologies, including organic photodiodes (OPD), advanced sensors capable of measuring biometric data such as heart rate and blood pressure directly from light generated by a panel touched by a patient, and a high-resolution microdisplay that delivers 5,000 PPI in a compact 1.4-inch form factor.

Intel is officially stepping back from its Deep Link suite of technologies. The confirmation came through a company representative on GitHub, confirming that active development has ceased. This follows a period when Intel quietly stopped highlighting Deep Link in newer offerings, such as its "Battlemage" GPUs. While the features might still work for those currently using Deep Link, don't expect any future updates or official assistance from Intel's support channels. If you cast your mind back to late 2020, you might recall Intel launching Deep Link. The core idea was to get Intel CPUs and their dedicated Arc GPUs working more effectively in tandem. To tap into this, you needed a specific setup: an 11th, 12th, or 13th Generation Intel CPU alongside an Arc Alchemist GPU. The package featured key tools: Dynamic Power Share for optimizing power between the CPU and GPU, Stream Assist to offload streaming to integrated graphics, Hyper Encode for faster video encoding, and Hyper Compute to accelerate AI tasks using OpenVINO.

These were designed to give a leg up to applications like OBS, DaVinci Resolve, and Handbrake. However, the writing may have been on the wall for Deep Link. Intel's "Meteor Lake" chips, which arrived in late 2023, weren't on the compatibility list, hinting that development had already wound down. Getting these features to perform reliably wasn't always straightforward, with users, like the one on GitHub who raised the initial question, reporting difficulties even with supported hardware. A user tried running Core Ultra 200S with Battlemage in OBS, facing issues not by the software, but by Intel's drivers. The general thinking is that Intel might have viewed Deep Link as a bit of a niche feature, possibly concluding that the continued effort and investment, especially with the need for validation with each software vendor, wasn't paying off. As for what's next, Intel hasn't announced a direct successor to these specific integrated features.

NEO Semiconductor, a leading developer of innovative technologies for 3D NAND flash memory and 3D DRAM, announced today the latest advancement in its groundbreaking 3D X-DRAM technology family—the industry-first 1T1C- and 3T0C-based 3D X-DRAM cell, a transformative solution designed to deliver unprecedented density, power efficiency, and scalability for the most demanding data applications.

Built on a 3D NAND-like architecture and with proof-of-concept test chips expected in 2026, the new 1T1C and 3T0C designs combine the performance of DRAM with the manufacturability of NAND, enabling cost-effective, high-yield production with densities up to 512 Gb—a 10x improvement over conventional DRAM.
"With the introduction of the 1T1C and 3T0C 3D X-DRAM, we are redefining what's possible in memory technology," said Andy Hsu, Founder & CEO of NEO Semiconductor. "This innovation pushes past the scaling limitations of today's DRAM and positions NEO as a frontrunner in next-generation memory."

Taiwan's electronics manufacturing services (EMS) providers are accelerating their North American production plans in response to tariff threats, but component shortages and capacity constraints at US chip plants could hamper the AI server market for years, according to industry sources.

"Since Trump's election, Taiwanese manufacturers have been strategically expanding their US presence," said Yen Chou, an analyst at DIGITIMES Research. "Most server manufacturers are concentrating in Texas, with Foxconn's FII already operating there and planning expansions."

Astera Labs, Inc., a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure, today announced its purpose-built PCIe 6 connectivity portfolio is ramping production to fast-track deployments of modern AI platforms at scale. Now featuring gearbox connectivity solutions alongside fabric switches, retimers, and active cable modules, Astera Labs' expanding PCIe 6 portfolio provides a comprehensive connectivity platform to deliver unparalleled performance, utilization, and scalability for next-generation AI and general-compute systems. Along with Astera Labs' demonstrated PCIe 6 connectivity over optical media, the portfolio will provide even greater AI rack-scale distance optionality. The transition to PCIe 6 is fueled by the insatiable demand for higher compute, memory, networking, and storage data throughput, ensuring advanced AI accelerators and GPUs operate at peak efficiency.

Thad Omura, Chief Business Officer, said, "Our PCIe 6 solutions have successfully completed qualification with leading AI and cloud server customers, and we are ramping up to volume production in parallel with their next generation AI platform rollouts. By continuing to expand our industry-leading PCIe connectivity portfolio with additional innovative solutions that includes Scorpio Fabric Switches, Aries Retimers, Gearboxes, Smart Cable Modules, and PCIe over optics technology, we are providing our hyperscaler and data center partners all the necessary tools to accelerate the development and deployment of leading-edge AI platforms."

China is pushing forward with its HBM (High Bandwidth Memory) progress as part of its plan to be self-sufficient in the semiconductor industry. JCET Group, China's top semiconductor packaging firm, has bought advanced TC (thermal compression) bonders that are usually used for 12-high stacks of HBM3E chips, according to Money Today Korea (MTN). This state-of-the-art equipment comes from Korean companies where export rules are less strict. This lets China jump from its current HBM2 technology to more advanced memory solutions. However, even if China isn't yet going to produce HBM3E chips soon, having this equipment is useful to boost manufacturing yields even for lower-spec HBM products.

China's desire to make HBM chips at home is a reaction to U.S. rules and taxes meant to hold back its chip abilities. These steps haven't slowed progress; instead, they have made China more determined to stand on its own in chip-making. The AI chip design market hit $18.4 billion last year and is set to grow 28% each year until 2032. The plan aims to supply Chinese-made HBM chips to big tech firms like Huawei, Tencent, and DeepSeek. This helps China get around U.S. export limits while moving its chip industry up in value. Choi Jae-hyeok, Professor of Electrical and Information Engineering, Seoul National University says, "In China's case, it is government-led... In the case of DDR, they are making up to DDR4 and DDR5. China has always wanted to move from low-value-added products to high-value-added products. The next direction is HBM..."

LG Display, the world's leading innovator of display technologies, announced today that it has become the world's first company to successfully verify the commercialization-level performance of blue phosphorescent OLED panels on a mass production line. The achievement comes about eight months after the company partnered with UDC to develop blue phosphorescence, and is considered a significant step closer to realizing a "dream OLED" display.

In the display industry, "dream OLED" refers to an OLED panel that achieves phosphorescence for all three primary colors of light (red, green, and blue). OLED panel light emission methods are broadly categorized into fluorescence and phosphorescence. Fluorescence is a simpler process in which materials emit light immediately upon receiving electrical energy, but its luminous efficiency is only 25%. In contrast, phosphorescence briefly stores received electrical energy before emitting light. Although it is technically more complex, this method offers luminous efficiency of 100% and uses a quarter as much power as fluorescence.

Siemens Digital Industries Software today announced that its continued collaboration with Intel Foundry has resulted in multiple product certifications, updated foundry reference flows, and additional technology enablement leveraging the foundry's leading-edge technologies for next-generation integrated circuits (IC) and advanced packaging. Siemens is a founding partner of the Intel Foundry Accelerator Chiplet Alliance - enabling a new and compelling solution for 3D IC and chiplet offerings to a breadth of semiconductor market verticals.

Intel 18A Certification Achievements
Siemens' industry-leading Calibre nmPlatform tool is now certified for the latest Intel 18A production Process Design Kit (PDK). Intel 18A represents a significant technological leap forward, featuring innovative RibbonFET Gate-all-around transistors and the industry's first PowerVia backside power delivery. This Calibre certification allows mutual customers to continue leveraging the Calibre nmPlatform tool as their industry-standard sign-off solution with Intel Foundry's most advanced manufacturing process, accelerating time-to-market for next-generation chip designs.

Seagate Technology Holdings plc (the "Company" or "Seagate"), a leading innovator of mass-capacity data storage, today reported financial results for its fiscal third quarter ended March 28, 2025.

"Seagate delivered another solid quarter of profitable year-on-year growth and margin expansion, elevating our non-GAAP EPS to the top of our guidance range. Our performance underscores the structural enhancements we've made to our business model and healthy supply/demand environment for mass capacity storage," said Dave Mosley, Seagate's chief executive officer. "We remain focused on executing our HAMR product ramp to support ongoing cloud customer demand. While we navigate the current dynamic macroeconomic environment, we are confident that our technology leadership, resilient financial model and solid industry fundamentals will drive profitable growth through 2025 and beyond," Mosley concluded.

Ansys today announced thermal and multiphysics signoff tool certifications for designs manufactured with Intel 18A process technology. These certifications help ensure functionality and reliability of advanced semiconductor systems for the most demanding applications—including AI chips, graphic processing units (GPUs), and high-performance computing (HPC) products. Intel Foundry and Ansys have also enabled a comprehensive multiphysics signoff analysis flow for Intel Foundry's EMIB technology used for creating multi-die 3D integrated circuit (3D-IC) systems.

Recognized as industry-leading solutions, RedHawk-SC and Totem deliver speed, accuracy, and capacity to analyze the power integrity and reliability of Intel 18A RibbonFET Gate-all-around (GAA) transistors with PowerVia backside power delivery. For scalable electromagnetic analysis, Ansys is introducing HFSS-IC Pro, a new addition to the HFSS-IC product family. HFSS-IC Pro is certified for modeling on-chip electromagnetic integrity in radio frequency chips, Wi-Fi, 5G/6G, and other telecommunication applications made with the Intel 18A process node.

Today at Intel Foundry Direct Connect, the company will share progress on multiple generations of its core process and advanced packaging technologies. The company will also announce new ecosystem programs and partnerships, and welcome industry leaders to discuss how a systems foundry approach enables collaboration with partners and unlocks innovation for customers.

Intel CEO Lip-Bu Tan will open the event by discussing Intel Foundry's progress and priorities as the company drives the next phase of its foundry strategy. Naga Chandrasekaran, Intel Foundry chief technology and operations officer, and Kevin O'Buckley, general manager of Foundry Services, will also deliver keynotes during the morning session, sharing process and advanced packaging news while highlighting Intel Foundry's globally diverse manufacturing and supply chain.

xMEMS Labs, Inc., the pioneer of monolithic MEMS-based solutions, today announced the expansion of its revolutionary µCooling fan-on-a-chip platform into AI data centers, bringing the industry's first in-module active thermal management solution to high-performance optical transceivers.

Originally developed for compact mobile devices, xMEMS µCooling now provides targeted, hyper-localized active cooling for dense, thermally-challenged environments inside 400G, 800G, and 1.6T optical transceivers—a critical yet underserved category in next-gen AI infrastructure.

Today IBM announced plans to invest $150 billion in America over the next five years to fuel the economy and to accelerate its role as the global leader in computing. This includes an investment of more than $30 billion in research and development to advance and continue IBM's American manufacturing of mainframe and quantum computers.

"Technology doesn't just build the future—it defines it," said Arvind Krishna, IBM chairman, president and chief executive officer. "We have been focused on American jobs and manufacturing since our founding 114 years ago, and with this investment and manufacturing commitment we are ensuring that IBM remains the epicenter of the world's most advanced computing and AI capabilities."

OKI Circuit Technology, the OKI Group printed circuit board (PCB) company, has successfully developed 124-layer PCB technology for wafer inspection equipment designed for next-generation high bandwidth memory, such as HBM mounted on AI semiconductors. This is a roughly 15% increase in the number of layers over conventional 108-layer designs. OTC is seeking to establish mass production technology by October 2025 at its Joetsu Plant in Joetsu City, Niigata Prefecture, which has a proven track record and advanced development and production capabilities in the field of high multilayer, high-precision, large-format PCBs for semiconductor inspection equipment.

AI processing requires the transmission of vast data volumes between graphics processing unit (GPU) semiconductors and memory. As semiconductor performance increases, the memory installed is also required to have high-speed, high-frequency, and high-density data transfer capabilities. HBM features a stacked DRAM structure, requiring technology capable of fabricating wafers even more thinly and precisely. This configuration also requires that the PCBs used in inspection equipment meet even higher levels of performance and quality.

Facing global challenges of energy conservation, carbon reduction, and sustainable development, Intel has been committed to pushing the industry toward higher performance and lower energy consumption product standards, actively leading the PC ecosystem toward a dual track of environmental protection and innovation. FSP Group, as Intel's long-term strategic development partner, shares the same philosophy and has continuously invested in power supply technology innovation with Intel's support, particularly focusing on 12VO architecture design that complies with the latest energy efficiency regulations.

At the Intel Client Ecosystem Symposium, FSP showcased its latest V3 version of TFX 12VO PSU, which not only helps brand customers build compliant PC systems but also contributes to carbon reduction and environmental protection with a design that balances high performance and energy efficiency.

M31 Technology Corporation (M31), a global provider of silicon intellectual property (IP), today announced that its eUSB2 PHY IP has achieved silicon-proven status on TSMC's 3 nm process and has successfully completed tape-out on TSMC's 2 nm process. As a member of TSMC Open Innovation Platform (OIP) IP Alliance since 2012, M31 has been honored with TSMC OIP Partner of the Year Award for seven consecutive years. In 2020, M31 pioneered its eUSB2 IP solution on the TSMC 7 nm process node, further solidifying its leadership in advanced interface IP development. Since then, M31 has steadily expanded its eUSB2 IP portfolio across TSMC's 5 nm, 3 nm, and most recently, 2 nm process technologies—closely aligning with TSMC's cutting-edge roadmap to accelerate the adoption of AI-enabled smart devices. Looking ahead, M31 is actively developing the next-generation eUSB2 Version 2.0 (eUSB2V2) PHY IP, with ongoing efforts focused on both TSMC's 3 nm and 2 nm process nodes.

Reinforcing its robustness and reliability on advanced nodes, M31's eUSB2 IP solutions have been widely adopted by leading global companies in high-end smartphone chipsets and AI-driven image processing applications. Building on this success, M31 is currently advancing the development of eUSB2V2 IP on TSMC's N3 and N2 process technologies - expanding its comprehensive eUSB2 portfolio to include eUSB2 V1, V2 PHY, and eUSB2 Repeater solutions. Leveraging the eUSB2 standard, eUSB2V2 enhances data transfer rates while maintaining a low-voltage interface and leveraging asymmetric bandwidth technology—allowing TX and RX to operate at different data rates. This significantly improves transmission efficiency, making it ideal for embedded applications such as AI edge computing, smart surveillance, and image processing chips. To accommodate diverse design needs, eUSB2V2 leverages and enhances the I/O architecture based on the eUSB2 standard, supporting data transfer speeds from 480 Mbps up to 4.8 Gbps. The solution delivers a comprehensive eUSB2 platform for high-end SoCs—optimizing power efficiency, performance and design flexibility, while maintaining full compatibility with legacy USB 2.0 devices.

TSMC today unveiled its next cutting-edge logic process technology, A14, at the Company's North America Technology Symposium. Representing a significant advancement from TSMC's industry-leading N2 process, A14 is designed to drive AI transformation forward by delivering faster computing and greater power efficiency. It is also expected to enhance smartphones by improving their on-board AI capabilities, making them even smarter. Planned to enter production in 2028, the current A14 development is progressing smoothly with yield performance ahead of schedule.

Compared with the N2 process, which is about to enter volume production later this year, A14 will offer up to 15% speed improvement at the same power, or up to 30% power reduction at the same speed, along with more than 20% increase in logic density. Leveraging the Company's experience in design-technology co-optimization for nanosheet transistor, TSMC is also evolving its TSMC NanoFlex standard cell architecture to NanoFlex Pro, enabling greater performance, power efficiency and design flexibility.

Avicena, headquartered in Sunnyvale, CA, announced today that the company will work with TSMC to optimize photodetector (PD) arrays for Avicena's revolutionary LightBundle microLED-based interconnects. LightBundle supports > 1Tbps/mm shoreline density and extends ultra-high density die-to-die (D2D) connections to > 10 meters at class-leading sub-pJ/bit energy efficiency. This will enable AI scale-up networks to support large clusters of GPUs across multiple racks, eliminating reach limitations of current copper interconnects while drastically reducing power consumption.

Increasingly sophisticated AI models are driving an unprecedented surge in demand for compute and memory performance, requiring interconnects with higher density, lower power, and longer reach for both processor-to-processor (P2P) and processor-to-memory (P2M) connectivity.

Today, NVIDIA confirmed that its Deep Learning Super Sampling technology (DLSS) boasts native support in 769 games and applications, reinforcing its lead over competing upscaling suites from AMD and Intel. With the addition of six newly announced titles, including the open‑world survival MMO RuneScape: Dragonwilds, DLSS's ecosystem continues to expand rapidly. Since its debut alongside the RTX 20 series in 2018, DLSS has evolved from a single AI‑powered upscaling method into a comprehensive toolkit. The current DLSS 4 iteration introduces Multi‑Frame Generation (MFG) and DLSS Transformers, delivering sharper images and smoother frame rates than earlier convolutional neural network modes. On supported RTX 40‑ and 50‑series GPUs, gamers can now take advantage of frame generation, denoising enhancements via ray reconstruction, and AI‑driven anti‑aliasing.

Of the six titles highlighted in NVIDIA's latest blog post, Steel Seed from Storm in a Teacup is the first to ship with DLSS 4's MFG. RuneScape: Dragonwilds, The Talos Principle: Reawakened, and Tempest Rising have added DLSS 3's frame‑generation and Super Resolution features, while indie releases Clair Obscur: Expedition 33 and Commandos: Origins deploy DLSS 2's Super Resolution alone. These incremental rollouts demonstrate how studios of all sizes are integrating NVIDIA's upscaling techniques at varying depths. By contrast, AMD's FidelityFX Super Resolution (FSR) and Intel's Xe Super Sampling (XeSS) toolkits support 356 and 161 titles, respectively. While AMD's FSR 4.0 can override older versions, its adoption remains focused on basic upscaling without frame generation, and XeSS continues to trail in overall scope. NVIDIA's manual override in its GeForce Experience app further widens the gap, allowing engineers to retrofit MFG into titles whose developers have yet to implement it natively.

Cadence today announced the industry's first DDR5 12.8 Gbps MRDIMM Gen 2 memory IP system solution on the TSMC N3 process. The new solution addresses the need for greater memory bandwidth to accommodate unprecedented AI processing demands in enterprise and data center applications, including AI in the cloud. The Cadence DDR5 MRDIMM IP boasts a new high-performance, scalable and adaptable architecture based on Cadence's proven and highly successful DDR5 and GDDR6 product lines. With multiple engagements underway with leading AI, HPC and data center customers, this IP solution is already demonstrating its early leadership.

The new Cadence DDR5 IP offers a PHY and a high-performance controller as a complete memory subsystem. The design is validated in hardware using the most recently available MRDIMMs (Gen 2), achieving a best-in-class 12.8 Gbps data rate that doubles the bandwidth using current DDR5 6400 Mbps DRAM parts. The DDR5 IP memory subsystem is based on Cadence's silicon-proven, high-performance architecture, ultra-low latency encryption and industry-leading RAS features. The DDR5 MRDIMM Gen 2 IP is designed to enable advanced SoCs and chiplets with flexible floor plan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements.