Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, today announced the successful tapeout of the industry's leading 64 Gbps UCIe die-to-die (D2D) IP subsystem on TSMC's 3 nm process technology. Building on its 36 Gbps Gen 2 silicon success, this third-generation subsystem delivers a major advancement in performance and shoreline bandwidth density for the IP Ecosystem. With 64 Gbps per-lane uni-directional data rates, it enables the next generation of chiplet-based architectures for AI, XPUs, and data center systems, providing power-efficient, reliable multi-die SoC integration and seamless interoperability across the chiplet ecosystem.

As the first 64 Gbps UCIe IP subsystem implemented on TSMC's 3 nm process, this achievement positions Alphawave Semi as a leader in UCIe die-to-die connectivity technology. With enhanced 64 Gbps UCIe performance and reduced power consumption, the solution enables new applications, including optical connectivity for Co-Packaged Optics (CPO), which are essential for scalable systems and environments requiring high lane count radix. Furthermore, it expands D2D interconnect capabilities, supporting a custom memory interface that delivers very low power and latency with a unique form factor, offering eight times greater bandwidth density compared to conventional memory interfaces.

Sarcina Technology, a pioneer in semiconductor and photonic package design, has announced the development of patented methodologies for the UCIe-A (Universal Chiplet Interconnect Express-Advanced) and UCIe-S (Standard) protocols. The company's latest innovations include an optimized RDL (redistribution layer) interposer design for die-to-die interconnections, supporting data rates up to 32 gigabits transfers per second (GT/s) whilst optimizing signal routing architecture to minimize crosstalk and maximize signal integrity.

As AI workloads continue to expand at an unprecedented pace, the semiconductor industry faces the dual challenge of performance and manufacturability. Traditional SoCs are approaching their limits in terms of size, yield and cost. The solution lies in chiplet-based architectures. Sarcina Technology is focused on enabling package design to achieve the system level performance required for next-generation AI systems.

Universal Chiplet Interconnect Express (UCIe) Consortium, the open standard for interconnects between chiplets within a package, today announced the release of the UCIe 3.0 specification, marking the next stage in the evolution of its open chiplet standard. The new specification delivers significant performance enhancements, most notably support for 48 GT/s and 64 GT/s data rates, alongside incremental architectural updates to meet growing industry demand for high-speed, interoperable chiplet solutions.

The UCIe 3.0 specification also introduces enhancements such as runtime recalibration for improved power efficiency and extended sideband reach that supports more flexible multi-chip configurations. Additional manageability features like early firmware download and priority sideband packets increase system responsiveness and reliability. The specification's optional manageability features give companies the flexibility to implement only what they need, enabling broad adoption while allowing design customization without unnecessary silicon.