AMD recently announced the latest "Zen 3" and "Zen 2" new processors are coming to the market very soon for DIY users, which includes the ground-breaking AMD 3D V-Cache technology processor, the AMD Ryzen 7 5800X3D. Moreover, the mainstream Ryzen 7 5700X, Ryzen 5 5600, Ryzen 5 5500, Ryzen 5 4600G, Ryzen 5 4500, and Ryzen 3 4100 are all here for different levels of system builds.

MSI is committed to deliver gamers and creators the best experiences. This is why BIOS update is always great for most users. The latest AMD AGESA COMBO PI V2 1.2.0.6c BIOS was released for some MSI 500- and 400-series motherboards. The purpose of AGESA 1.2.0.6c is not only for better compatibility but also for maximizing AMD Ryzen 7 5800X3D performance. For the older 300-series motherboards, we will release the AGESA COMBO PI V2 1.2.0.6c beta BIOS by the end of April. Please refer to the following chart for more information.

TYAN, an industry-leading server platform design manufacturer and a MiTAC Computing Technology Corporation subsidiary, today announced availability of high-performance server platforms supporting new 3rd Gen AMD EPYC Processors with AMD 3D V-Cache technology for the modern data center. "The modern data center requires a powerful foundation to balance compute, storage, memory and IO that can efficiently manage growing volumes in the digital transformation trend," said Danny Hsu, Vice President of MiTAC Computing Technology Corporation's Server Infrastructure Business Unit. "TYAN's industry-leading server platforms powered by 3rd Gen AMD EPYC processors with AMD 3D V-Cache technology give our customers better energy efficiency and increased performance for a current and future of highly complex workloads."

"3rd Gen AMD EPYC processors with AMD 3D V-Cache technology continue to drive a new standard for the modern data center with breakthrough performance for technical computing workloads due to 768 MB of L3 cache, enabling faster time-to-results on targeted workloads. Fully socket compatible with our 3rd Gen AMD EPYC platforms, customers can adopt these processors to transform their data center operations to achieve faster product development along with exceptional energy savings," said Ram Peddibhotla, corporate vice president, EPYC product management, AMD.

Super Micro Computer, Inc. (SMCI), a global leader in high-performance computing, storage, networking solutions, and green computing technology, announces breakthrough performance with the 3rd Gen AMD EPYC Processors with AMD 3D V-Cache Technology in Supermicro advanced servers. The high density, performance-optimized, and environmentally friendly SuperBlade and multi-node optimized TwinPro and the dual-processor optimized Ultra systems will show significant performance improvement when using the new AMD EPYC 7003 Processors with AMD 3D V-Cache for technical computing applications.

"Supermicro servers, leveraging new AMD CPUs, will deliver the increased performance gains our manufacturing customers are looking for to run higher-resolution simulations to design better and more optimized products using the latest CAE applications," said Vik Malyala, President, EMEA, senior vice president, WW FAE, solutions and business. "Our high-performance server platforms will solve more complex problems for engineers and researchers with the new 3rd Gen AMD EPYC Processors with AMD 3D V-Cache."

AMD announced the general availability of the world's first data center CPU using 3D die stacking, the 3rd Gen AMD EPYC processors with AMD 3D V-Cache technology, formerly codenamed "Milan-X." Built on the "Zen 3" core architecture, these processors expand the 3rd Gen EPYC CPU family and can deliver up to 66 percent performance uplift across a variety of targeted technical computing workloads versus comparable, non-stacked 3rd Gen AMD EPYC processors.

These new processors feature the industry's largest L3 cache delivering the same socket, software compatibility and modern security features as 3rd Gen AMD EPYC CPUs while providing outstanding performance for technical computing workloads such as computational fluid dynamics (CFD), finite element analysis (FEA), electronic design automation (EDA) and structural analysis. These workloads are critical design tools for companies that must model the complexities of the physical world to create simulations that test and validate engineering designs for some of the world's most innovate products.

In a livestream talking about AMD's mobile CPUs with HotHardware, Robert Hallock shone some light on the rumours about the Ryzen 7 5800X3D lacking manual overclocking. As per earlier rumours, something TechPowerUp! confirmed with our own sources, AMD's Ryzen 7 5800X3D lacks support for manual CPU overclocking and AMD asked its motherboard partners to remove these features in the UEFI. According to the livestream, these CPUs are said to be hard locked, so there's no workaround when it comes to adjusting the CPU multiplier or Voltage, but at least AMD has a good reason for it.

It turns out that the 3D V-Cache is Voltage limited to a maximum of 1.3 to 1.35 Volts, which means that the regular boost Voltage of individual Ryzen CPU cores, which can hit 1.45 to 1.5 Volts, would be too high for the 3D V-Cache to handle. As such, AMD implemented the restrictions for this CPU. However, the Infinity Fabric and memory bus can still be manually overclocked. The lower Voltage boost also helps explain why the Ryzen 7 5800X3D has lower boost clocks, as it's possible that the higher Voltages are needed to hit the higher frequencies.

TechPowerUp has verified a rumour posted over on VideoCardz that is quite puzzling, as AMD has asked motherboard makers to remove support for overclocking in the UEFI/BIOS for the Ryzen 7 5800X3D. When we asked for a reason as to why this was the case, we were told that AMD was keeping that information to themselves for the time being. The details provided by AMD are short and to the point "5800X3D 8C16T 100-xxxxxxxxx 105 W AGESA: PI 1206b 1/28 Please hide Vermeer-X CPU OC BIOS SETUP options".

The information suggests that this happened back at the end of January, although it's no surprise that this information took some time to leak, as it's not the kind of information that would normally make its way outside of the motherboard manufacturers. AGESA 1.2.0.6 B is also the most current release for a wide range of motherboards, even though it doesn't seem to be offered as a final release from all of the board makers just yet. It's unclear why AMD has done this, but it suggests that there might be some issues related to the 3D V-Cache and overclocking.

This week, the International Solid-State Circuits Conference is taking place online and during one of the sessions, AMD shared some more details of its 3D V-Cache design. The interesting part here is the overall design of AMD's 3D V-Cache, as well as how it interfaces with its CPU dies. The cache chip itself is said to measure 36 mm² and interfaces directly with the L3 cache using a Through Silicon Via or TSV interface. For all the CPU cores to be able to communicate with the 3D V-Cache, AMD has implemented a shared ring bus design at the L3 level. The entire L3 cache is said to be available to each of the cores, which should further help improve performance.

The 3D V-Cache is made up of multiple 8 MB "slices" which has a 1,024 contact interface with a single CPU core, for a total of 8,192 connections in total between the CCX and the 3D V-Cache. This allows for a bandwidth in excess of two terabyte per second, per slice, in full duplex mode. This should allow for full L3 speeds for the 3D V-Cache, despite the fact that it's not an integrated part of the CCX. AMD is also said to have improved the design of its CCX for the upcoming Ryzen 7 5800X3D in several ways to try and reduce the power draw, while improving clock speeds. AMD has yet to reveal a launch date for the Ryzen 7 5800X3D, but it'll be interesting to see if the 3D V-Cache and the various minor optimizations can make it competitive with Intel's Alder Lake CPUs until Zen 4 arrives.

The AMD Milan-X EPYC 7773X 3D V-Cache is a 64-core, 128-thread server processor with 804 MB of cache that is currently shipping to global data centers. These processors are not yet officially available in retail channels but Chinese content creator kenaide has managed to acquire and test two qualification sample chips on a SuperMicro dual-socket motherboard. The AMD EPYC 7773X is detected as 100-000000504-04 CPU by CPU-Z confirming that it's an engineering sample with clock speeds 100 MHz below the 2.2 GHz and 3.5 GHz base and boost speeds of the official processor.

The processors each feature 32 MB L2, 256 MB L3, and 512 MB of 3D V-Cache for a total of 1608 MB cache in the configuration that was benchmarked with Cinebench R23 and 3DMark. The processors were also "overclocked" to 4.8 GHz using the EPYC Milan/Rome ES/QS Overclocking tool by increasing their power limit to 1500 W from 280 W and boosting the voltage to 1.55 V. This 4.8 GHz clock speed is only a target with the actual speed reached not reported and no benchmarks for the overclocked processors shared.

AMD (NASDAQ:AMD) today announced revenue for the fourth quarter of 2021 of $4.8 billion, operating income of $1.2 billion, net income of $974 million and diluted earnings per share of $0.80. On a non-GAAP basis, operating income was $1.3 billion, net income was $1.1 billion and diluted earnings per share was $0.92. For full year 2021, the company reported revenue of $16.4 billion, operating income of $3.6 billion, net income of $3.2 billion and diluted earnings per share of $2.57. On a non-GAAP basis, operating income was $4.1 billion, net income was $3.4 billion and diluted earnings per share was $2.79.

"2021 was an outstanding year for AMD with record annual revenue and profitability," said AMD President and CEO Dr. Lisa Su. "Each of our businesses performed extremely well, with data center revenue doubling year-over-year driven by growing adoption of AMD EPYC processors across cloud and enterprise customers. We expect another year of significant growth in 2022 as we ramp our current portfolio and launch our next generation of PC, gaming and data center products."

AMD via its official YouTube has shared a video that goes into slightly more detail on their usage of V-Cache on the upcoming Zen 3+ CPUs. Firstly demoed to the public on AMD's Computex 2021 event, the 3D V-Cache leverages TSMC's SoIC stacking technology, which enables silicon developments along the Z axis, instead of the more usual footprint increase along the X axis. The added 3D V-Cache, which was shown in Computex as being deployed in a prototype Ryzen 9 5900X 12-core CPU, adds 64 MB of L3 cache to each CCX (the up-to-eight-cores core complex on AMD's latest Zen design), basically tripling the amount of L3 cache available for the CPU. This, in turn, was shown to increase FPS in games quite substantially (somewhere around 15%), as games in particular are sensitive to this type of CPU resources.

The added information explains that there is no usage of microbumps - instead, there is a perfect alignment between the bottom layer (with the CCX) and the top layer (the L3 cache) which enables the bonding process to occur naturally via the TSVs (Through Silicon Vias) already present in the silicon, in a zero-gap manner, between both halves of the CPU-cache sandwich. To enable this, AMD flipped the CCX upside down (the core complex now faces the bottom of the chip, instead of the top), shaved 95% of the silicon on top of the upside-down core complexes, and then attaches the 3D V-Cache chips on top of this formation. This also has the added bonus of decreasing the distance between the L3 cache and the CCX (the distance between both in the Z axis is around 1,000 times smaller than if the L3 cache was deployed in the classical X axis), which decreases power consumption, temperatures, and latency, allowing for further increases to system performance. Look after the break for the full video.