Last autumn, AMD provided an update regarding developmental progress of its openSIL open-source project. According to Raj Kapoor's presentation at last year's OCP Global Summit, the Red Team intends to publish its sixth-generation "Zen 6"-based EPYC "Venice" CPU openSIL sources at some point in 2026. The company's lead firmware architect reiterated that the newer silicon-initialization stack will eventually replace the familiar legacy AGESA firmware line. As of last summer, only one section of AMD's "Zen 5" family has received openSIL support—the EPYC 9005 "Turin" server processor product range. Earlier this week, a 3mbdeb blog entry detailed a compelling experiment that involved the initial "enabling (of) AMD AM5 'Phoenix' support in Coreboot." In the past, this Polish open-source consulting company has experimented with unusual ports of OpenSIL and Coreboot (via the Dasharo distribution). NLnet Foundation funding provided a secure base to start 3mbdeb's Gigabyte MZ33-AR1 porting project, leading to present-day tinkering with MSI's PRO B850-P consumer-grade mainboard design.

Mid-way through their post, they detail a handful of problems, including: "some issues may arise when parsing combo images for AM5 desktop platforms. The desktop images are more complex than server ones. A single PSP (Platform Security Processor) directory may support multiple CPU families, whereas on servers, each CPU family required separate PSP directory. This adds complexity, a need to distinguish PSP directories from each other, and determine the supported CPUs by given directory." So far, the MSI B850-P Pro-based tests have reached a phase of development that is "just enough to (achieve) boot." When outlining a next major milestone, 3mbdeb intends to: "add basic support for desktop AM5 'Phoenix' platform to distinguish mobile CPUs from desktop CPUs in Coreboot. This will serve as a base to cover the differences between the mobile and desktop Phoenix SoCs/APUs." They stress that their 'Phoenix' OpenSIL project is still in a "Proof of Concept" stage, so "not intended for production use." In summary, 3mbdeb's firmware engineer (Michał Żygowski) recommends that external testers wait for the arrival of "exciting" future releases.

AMD used the Open Compute Project Global Summit in San Jose to provide an update on openSIL, its initiative to replace the legacy AGESA firmware with an open silicon-initialization stack, with timelines for CPUs based on the "Zen 6" IP. Chief Firmware Architect Raj Kapoor presented the latest developments and confirmed that slides and a video of the talk are now available to the public. As part of the update, AMD released the openSIL Firmware Architecture Specification 1.0 and initial platform code for its "Phoenix" client SoCs, marking a shift from proof-of-concept work to wider platform availability. Kapoor also outlined a practical release schedule for future platforms. AMD reiterated that it will initially keep some platform sources under NDA until product launch, then release open-source platform code approximately one quarter after shipping.

According to this schedule, AMD plans to publish the "Venice" 6th Gen EPYC openSIL sources in 2026, suggesting a Venice product launch by Q3 in 2026, and to release the "Medusa" Ryzen CPUs based on "Zen 6" sources in the first half of 2027. The openSIL is designed as a modular, three-part static library written to modern C standards, intended to integrate seamlessly with any x86 host firmware while remaining scalable for different customer needs. Beyond timelines and deliverables, AMD envisioned openSIL as an effort to enhance transparency, speed up integration for hyperscalers, and improve security through auditable code. The project will allow public pull requests, although contributions will be reviewed to protect sensitive microarchitectural IP. This balance between openness and protection was a recurring theme in the presentation, as AMD seeks to open more of its firmware for community collaboration while managing to expose just enough of core design details that drive its CPUs.

AMD's openSIL project, a solution for open CPU silicon initialization code aimed at replacing traditional AGESA, has reached another milestone. Back in February, we reported on AMD promising full support for "Turin" and "Phoenix" server and client SoCs. The company initially targeted the end of 2024 for the release of proof-of-concept code, but failed to meet this deadline. A new target was subsequently set for the first half of 2025. As we roll into the second half, AMD openSIL now supports only the EPYC 9005 series Turin server processors, with Phoenix client SoCs still in development. AMD firmware engineers explained: "Currently, the Phoenix openSIL PoC release is still being worked on internally at AMD. We have encountered some delays in obtaining the necessary approvals to open-source the code, which has impacted our timeline. We are actively working to resolve these issues and are making every effort to expedite the process."

The path towards a fully open-source silicon initialization code is difficult, as it can expose many microarchitectural details. These are usually closely protected, as IP from Zen cores is valuable. An AMD engineer also added, "We understand the importance of this project to the open-source community and are committed to delivering it as promised." Nonetheless, the primary goal remains achieving full production readiness with the upcoming Zen 6 architecture. The openSIL project promises to enhance Coreboot support and provide developers with full access to low-level system components.

AMD's openSIL project, aimed towards open CPU silicon initialization code, continues progressing despite a slight delay in its development timeline. The initiative, which will eventually replace the current AGESA system across AMD's client and server processors, received a new update. The company initially targeted the end of 2024 to release proof-of-concept code for Phoenix client SoCs and Turin server hardware. However, as we move through the first quarter of 2025, AMD has acknowledged a slight deviation from this schedule. In a recent statement, AMD representatives assured the developer community that work continues steadily on both Phoenix and Turin proof-of-concept releases.

"We are hard at work preparing the Phoenix and Turin POC's for public release," stated an AMD representative, emphasizing that these releases will serve as sample code previewing future production-worthy implementations. The company clarified that these initial releases are not intended for production environments. The delay has minimal impact on AMD's plan, as the primary goal remains focused on achieving full production readiness with the upcoming Zen 6 architecture. The openSIL project promises to enhance Coreboot support and provide developers with full access to low-level system components. Though limited to select reference motherboards, the proof-of-concept releases will serve as the first milestones in AMD's journey toward more open hardware solutions.

OpenSIL is an open-source CPU initialization framework project that seeks to replace on-chip initialization microcode, such as AGESA, across both client- and server processors. AMD looks to implement OpenSIL as it makes its AMD EPYC processors more friendly to large customers that want to take control of this aspect of the processor. Since its open-sourcing in June 2023, AMD has come up with reference motherboards implementing OpenSIL, as well as modifying a Supermicro server motherboard to the architecture, to demo at conferences. AMD firmware engineer Paul Grimes presented the company's progress with implementing OpenSIL, at the OSFC conference, in Germany. It's been known that AMD is targeting a 2025-26 timeline for OpenSIL to hit product, but AMD put out specifics, such as its next-generation "Venice" server processor supporting OpenSIL.

"Venice" is codename for an AMD EPYC server processor generation succeeding "Turin." It is built on the future "Zen 6" microarchitecture, and AMD could at least unveil the processor some time in 2025, if not mass-produce it. late-2024 thru 2025 could see the company ramp up "Turin" and other server processors implementing "Zen 5." That's not all, AMD plans to being OpenSIL even to client processors, with the generation of Ryzen processors based on "Zen 6." This will see the AGESA microcode replaced by a first-party firmware from AMD based on OpenSIL, which PC OEMs will be able to customize. The biggest impact of this change will be felt in the commercial notebook and commercial desktop segments, where large organizations can take greater control over the chip initialization firmware.

During the OCP Regional Summit, AMD has shared plans to replace AGESA with openSIL. The change will not come soon, and according to details, it will be a slow process starting in 2026. AGESA firmware updates are quite important but also vulnerable to cyber-attacks, which is one of the key points for the new OpenSIL, which is proposed as an open-source solution.

As detailed by Phoronix, AMD mentioned the Open-Source Silicon Initialization Library (openSIL) back in mid-April, when it launched initial support for 4th Gen EPYC processors and its reference platform. Although initially aimed at server processors, AMD has made clear during the OCP presentation that the OpenSIL is meant to be a replacement to AMD Generic Encapsulated Software Architecture (AGESA), covering the entire product stack. As said, AMD plans for openSIL to be simple, easily scalable, lightweight, and open-source, thus increasing the overall security.