Thursday, October 30th 2025
AMD openSIL Targets "Zen 6" Support in the First Half of 2027
AMD used the Open Compute Project Global Summit in San Jose to provide an update on openSIL, its initiative to replace the legacy AGESA firmware with an open silicon-initialization stack, with timelines for CPUs based on the "Zen 6" IP. Chief Firmware Architect Raj Kapoor presented the latest developments and confirmed that slides and a video of the talk are now available to the public. As part of the update, AMD released the openSIL Firmware Architecture Specification 1.0 and initial platform code for its "Phoenix" client SoCs, marking a shift from proof-of-concept work to wider platform availability. Kapoor also outlined a practical release schedule for future platforms. AMD reiterated that it will initially keep some platform sources under NDA until product launch, then release open-source platform code approximately one quarter after shipping.
According to this schedule, AMD plans to publish the "Venice" 6th Gen EPYC openSIL sources in 2026, suggesting a Venice product launch by Q3 in 2026, and to release the "Medusa" Ryzen CPUs based on "Zen 6" sources in the first half of 2027. The openSIL is designed as a modular, three-part static library written to modern C standards, intended to integrate seamlessly with any x86 host firmware while remaining scalable for different customer needs. Beyond timelines and deliverables, AMD envisioned openSIL as an effort to enhance transparency, speed up integration for hyperscalers, and improve security through auditable code. The project will allow public pull requests, although contributions will be reviewed to protect sensitive microarchitectural IP. This balance between openness and protection was a recurring theme in the presentation, as AMD seeks to open more of its firmware for community collaboration while managing to expose just enough of core design details that drive its CPUs.
According to this schedule, AMD plans to publish the "Venice" 6th Gen EPYC openSIL sources in 2026, suggesting a Venice product launch by Q3 in 2026, and to release the "Medusa" Ryzen CPUs based on "Zen 6" sources in the first half of 2027. The openSIL is designed as a modular, three-part static library written to modern C standards, intended to integrate seamlessly with any x86 host firmware while remaining scalable for different customer needs. Beyond timelines and deliverables, AMD envisioned openSIL as an effort to enhance transparency, speed up integration for hyperscalers, and improve security through auditable code. The project will allow public pull requests, although contributions will be reviewed to protect sensitive microarchitectural IP. This balance between openness and protection was a recurring theme in the presentation, as AMD seeks to open more of its firmware for community collaboration while managing to expose just enough of core design details that drive its CPUs.
10 Comments on AMD openSIL Targets "Zen 6" Support in the First Half of 2027
It's not like this serves AMD in any way. They (or TSMC) have issues, one way or another.
Nova Lake apparently is N2P (the compute tile) so that would mean AMD needs at least the same node if not better to win. Because I imagine their only goal is to win, and probably win decisively. They will win with the X3D models but the standard ones have to make a good impression too.
The thing is though that Zen6 delays have been rumored.
While it's still disgusting rumors, why would dual V-cache CPU's keep on popping up if AMD would launch Zen6 within 6 months? That's a band-aid while waiting for Zen6 if you're asking me.
www.techpowerup.com/342095/amd-could-launch-16-core-ryzen-9-9950x3d2-cpu-with-192-mb-l3-cache-and-200-w-tdp
Two years is the normal cadence these days for both CPU's and GPU's.That's assumed, that Zen 6 wont launch before OpenSIL is ready, but i doubt that's the case.Bad time. DDR5 prices have shot trough the roof and wont come down until the middle of 2026 at the earliest. So unless you already have DDR5...