Samsung's foundry plans have again hit a major setback. The company notified staff at its Taylor, Texas facility that it was temporarily removing workers from the site because it is still experiencing challenges with 2 nm semiconductor yields, delaying mass production timelines from late 2024 to 2026. The Taylor site had been anticipated as the flagship facility for Samsung's sub-4 nm production, allowing access to potential customers near the facility. While Samsung has moved rapidly in terms of process development, its yields for advanced nodes have outstripped them, the company's yields for sub-3 nm processes hover around 50%, with Gate-All-Around (GAA) technology witnessing yields of only 10-20%, significantly lower than neighboring competitor TSMC's 60-70% for corresponding nodes.

The yield gaps that the company is experiencing have exacerbated the gap in market share, with TSMC capturing 62.3% of the global foundry market share in Q2 versus Samsung's 11.5%. The company is struggling to gain share despite efforts by Chairman Lee Jae-yong - including visits to component suppliers ASML, and Zeiss - and these yields put at risk as much as 9 trillion won in U.S. CHIP Act potential subsidies that are dependent upon operational milestones.

According to a recent report from Bloomberg, Intel is in talks with investment banks about a possible spin-out of its foundry business, as well as scraping some existing expansion plans to cut losses. As the report highlights, sources close to Intel noted that the company is exploring various ways to deal with the recent Q2 2024 earnings report. While Intel's revenues are in decline, they are still high. However, the profitability of running its business has declined so much that the company is now operating on a net loss, with an astonishing $1.61 billion in the red. CEO Pat Gelsinger is now exploring various ways to control these losses and make the 56-year-old giant profitable again. Goldman Sachs and Morgan Stanley are reportedly advising Intel about its future moves regarding the foundry business and overall operations.

The Intel Foundry unit represents the biggest consumer of the company's funds, as the expansion plans across the US and Europe are costing Intel billions of US Dollars. Even though the company receives various state subsidies to build semiconductor manufacturing facilities, it still has to put much of its capital to work. Given that the company is running tight on funds, some of these expansion plans that are not business-critical may get scraped. Additionally, running the foundry business is also turning out to be rather costly, with Q2 2024 recording a negative 65.5% operating margin. Separating Intel Product and Intel Foundry may be an option, or even selling the foundry business as a whole is on the table. Whatever happens next is yet to be cleared up. During the Deutsche Bank Technology Conference on Thursday, Pat Gelsinger also noted that "It's been a difficult few weeks" for Intel, with many employees getting laid off to try to establish new cost-saving measures.

Texas Instruments (TI) (Nasdaq: TXN) and the U.S. Department of Commerce have signed a non-binding Preliminary Memorandum of Terms for up to $1.6 billion in proposed direct funding under the CHIPS and Science Act to support three 300 mm wafer fabs already under construction in Texas and Utah. In addition, TI expects to receive an estimated $6 billion to $8 billion from the U.S. Department of Treasury's Investment Tax Credit for qualified U.S. manufacturing investments. The proposed direct funding, coupled with the investment tax credit, would help TI provide a geopolitically dependable supply of essential analog and embedded processing semiconductors.

"The historic CHIPS Act is enabling more semiconductor manufacturing capacity in the U.S., making the semiconductor ecosystem stronger and more resilient," said Haviv Ilan, president and CEO of Texas Instruments. "Our investments further strengthen our competitive advantage in manufacturing and technology as we expand our 300 mm manufacturing operations in the U.S. With plans to grow our internal manufacturing to more than 95% by 2030, we're building geopolitically dependable, 300 mm capacity at scale to provide the analog and embedded processing chips our customers will need for years to come."

Samsung Electronics is set to make a significant leap in semiconductor manufacturing technology with the introduction of its first High-NA 0.55 EUV lithography tool. The company plans to install the ASML Twinscan EXE:5000 system at its Hwaseong campus between Q4 2024 and Q1 2025, marking a crucial step in developing next-generation process technologies for logic and DRAM production. This move positions Samsung about a year behind Intel but ahead of rivals TSMC and SK Hynix in adopting High-NA EUV technology. The system is expected to be operational by mid-2025, primarily for research and development purposes. Samsung is not just focusing on the lithography equipment itself but is building a comprehensive ecosystem around High-NA EUV technology.

The company is collaborating with several key partners like Lasertec (developing inspection equipment for High-NA photomasks), JSR (working on advanced photoresists), Tokyo Electron (enhancing etching machines), and Synopsys (shifting to curvilinear patterns on photomasks for improved circuit precision). The High-NA EUV technology promises significant advancements in chip manufacturing. With an 8 nm resolution capability, it could make transistors about 1.7 times smaller and increase transistor density by nearly three times compared to current Low-NA EUV systems. However, the transition to High-NA EUV comes with challenges. The tools are more expensive, costing up to $380 million each, and have a smaller imaging field. Their larger size also requires chipmakers to reconsider fab layouts. Despite these hurdles, Samsung aims for commercial implementation of High-NA EUV by 2027.

Japanese professor Tsumoru Shintake of the Okinawa Institute of Science and Technology (OIST) has unveiled a revolutionary extreme ultraviolet (EUV) lithography technology that promises to significantly push down semiconductor manufacturing costs. The new technology tackles two previously insurmountable issues in EUV lithography. First, it introduces a streamlined optical projection system using only two mirrors, a dramatic simplification from the conventional six or more. Second, it employs a novel "dual line field" method to efficiently direct EUV light onto the photomask without obstructing the optical path. Prof. Shintake's design offers substantial advantages over current EUV lithography machines. It can operate with smaller EUV light sources, consuming less than one-tenth of the power required by conventional systems. This reduction in energy consumption also reduces operating expenses (OpEx), which are usually high in semiconductor manufacturing facilities.

The simplified two-mirror design also promises improved stability and maintainability. While traditional EUV systems often require over 1 megawatt of power, the OIST model can achieve comparable results with just 100 kilowatts. Despite its simplicity, the system maintains high contrast and reduces mask 3D effects, which is crucial for attaining nanometer-scale precision in semiconductor production. OIST has filed a patent application for this technology, with plans for practical implementation through demonstration experiments. The global EUV lithography market is projected to grow from $8.9 billion in 2024 to $17.4 billion by 2030, when most nodes are expected to use EUV scanners. In contrast, ASML's single EUV scanner can cost up to $380 million without OpEx, which is very high thanks to the power consumption of high-energy light UV light emitters. Regular EUV scanners also lose 40% of the UV light going to the next mirror, with only 1% of the starting light source reaching the silicon wafer. And that is while consuming over one megawatt of power. However, with the proposed low-cost EUV system, more than 10% of the energy makes it to the wafer, and the new system is expected to use less than 100 kilowatts of power while carrying a cost of less than 100 million, a third from ASML's flagship.

Intel Corporation today announced the appointment of Dr. Naga Chandrasekaran as chief global operations officer, executive vice president and general manager of Intel Foundry Manufacturing and Supply Chain organization. Chandrasekaran joins Intel from Micron, where he served as senior vice president for Technology Development. He will be a member of Intel's executive leadership team and report to CEO Pat Gelsinger.

Chandrasekaran succeeds Keyvan Esfarjani, who has decided to retire from Intel after nearly 30 years of dedicated service. Esfarjani's distinguished career set a strong foundation for Intel Foundry, and his leadership in global supply chain resilience and manufacturing excellence has helped to position Intel's business for long-term success. He will remain with Intel through the end of the year to ensure a seamless transition.

A recent report from Taiwan TV News has revealed that TSMC's overseas expansion plans will only contribute around 10% of the company's total silicon production capacity. TSMC's overseas expansion strategy has been a topic of significant interest in the tech industry as the company seeks to diversify its manufacturing capabilities beyond its home base in Taiwan. The company has announced plans to build new fabrication plants in the United States, Japan, and potentially other regions in an effort to mitigate supply chain risks and better serve its global customer base. However, according to the report, these overseas facilities will only account for a small fraction of 10% of TSMC's overall production capacity.

The majority of the company's manufacturing will continue to be centered in Taiwan, where it maintains its most advanced and high-volume fabs. There are also significant challenges and investments required to establish new semiconductor manufacturing facilities overseas. Building a state-of-the-art fab can cost billions of dollars and take several years to complete, making it a complex and capital-intensive undertaking. Despite the relatively small contribution of its overseas facilities, TSMC's global expansion is still seen as a crucial step in diversifying its supply chain and mitigating geopolitical risks. The company's ability to maintain its technological leadership and meet the growing demand for advanced chips will be crucial in the years to come.

To keep pace with unremitting growth in demand for chips, the global semiconductor manufacturing industry is expected to increase capacity by 6% in 2024 and post a 7% gain in 2025, reaching a record capacity high of 33.7 million wafers per month (wpm: 8-inch equivalent), SEMI announced today in its latest quarterly World Fab Forecast report.

Leading-edge capacity for 5 nm nodes and under is expected to grow 13% in 2024, chiefly driven by generative artificial intelligence (AI) for data center training, inference, and leading-edge devices. To increase processing power efficiency, chipmakers including Intel, Samsung, and TSMC are poised to start production of 2 nm Gate-All-Around (GAA) chips, boosting total leading-edge capacity growth by 17% in 2025.

Micron Technology, Inc., one of the world's largest semiconductor companies and the only U.S.-based manufacturer of memory, and the Biden-Harris Administration today announced that they have signed a non-binding Preliminary Memorandum of Terms (PMT) for $6.1 billion in funding under the CHIPS and Science Act to support planned leading-edge memory manufacturing in Idaho and New York.

The CHIPS and Science Act grants of $6.1 billion will support Micron's plans to invest approximately $50 billion in gross capex for U.S. domestic leading-edge memory manufacturing through 2030. These grants and additional state and local incentives will support the construction of one leading-edge memory manufacturing fab to be co-located with the company's existing leading-edge R&D facility in Boise, Idaho and the construction of two leading-edge memory fabs in Clay, New York.

As a part of its Q1 earnings call discussion, one of the largest semiconductor manufacturers, TSMC, has unveiled a strategic move to charge a premium for chips manufactured at its newly established overseas fabrication plants. During an earnings call, TSMC's CEO, C.C. Wei, announced that the company will impose higher pricing for chips produced outside Taiwan to offset the higher operational costs associated with these international locations. This move aims to maintain TSMC's target gross margin of 53% amidst rising expenses such as inflation and elevated electricity costs. This decision comes as TSMC expands its global footprint with new facilities in the United States, Germany, and Japan (JAMS) to meet the increasing demand for semiconductor chips worldwide. The company's new US-based Arizona facility, known as Fab 21, has faced delays due to equipment installation issues and labor negotiations.

Chips produced at this site, utilizing TSMC's advanced N5 and N4 nodes, could cost between 20% to 30% more than those manufactured in Taiwan. TSMC's strategy to manage the cost disparities across different geographic locations involves strategic pricing, securing government support, and leveraging its manufacturing technology leadership. This approach reflects the company's commitment to maintaining its competitive edge while navigating the complexities of global semiconductor manufacturing in today's fragmented market. Introducing a location premium is expected to impact American semiconductor designers, who may need to pass these costs on to specific market segments, particularly those with lower price sensitivity, such as government-related projects. Despite these challenges, TSMC's overseas expansion underscores its adaptive strategies in the face of global economic pressures and industry demands, ensuring its continued position as a leading player in the semiconductor industry.

On March 29th, the United States announced another round of updates to its export controls, targeting advanced computing, supercomputers, semiconductor end-uses, and semiconductor manufacturing products. These new regulations, which took effect on April 4th, are designed to prevent certain countries and businesses from circumventing U.S. restrictions to access sensitive chip technologies and equipment. Despite these tighter controls, TrendForce believes the practical impact on the industry will be minimal.

The latest updates aim to refine the language and parameters of previous regulations, tightening the criteria for exports to Macau and D:5 countries (China, North Korea, Russia, Iran, etc.). They require a detailed examination of all technology products' Total Processing Performance (TPP) and Performance Density (PD). If a product exceeds certain computing power thresholds, it must undergo a case-by-case review. Nevertheless, a new provision, Advanced Computing Authorized (ACA), allows for specific exports and re-exports among selected countries, including the transshipment of particular products between Macau and D:5 countries.

At 07:58 local time, Taiwan was rocked by a magnitude 7.4 earthquake on the east coast which was felt nationwide and as far as to the southeastern parts of China and southern Japan. It caused some major damage in the east coast city of Hualien where the epicentre of the quake was located, as well as surrounding areas. The earthquake reportedly left nine people dead and over 900 people injured islandwide. TSMC, UMC, PSMC and Innolux all halted some of their production lines in the Hsinchu Science Park on the west coast of the island, although this is said to have been as a preventive step, rather than caused by actual damage from the earthquake.

All the above-mentioned companies also evacuated their staff from their factories due to the intensity of the quake, as it reached a magnitude of around four or five almost island wide. The semiconductor manufacturers are all inspecting their fabs now to make sure none of the equipment was damaged by the earthquake. Innolux also has a factory in the southern city of Kaohsiung and has reported that it has suspended production in Hsinchu, but that production in Kaohsiung wasn't affected. Local media in Taiwan hasn't made any mention of the likes of Micron or other chip manufacturers, but it's likely that the situation is similar, since all of these companies are located in the same areas on the island. Aftershocks have continued throughout the day and there's a risk for further big earthquakes to follow in the coming days.Images courtesy of the Taiwan Central Weather Administration (CWA).

Update 15:11 UTC: Updated with an official statement from Micron below.

"The Earth is Blue," said Yuri Gagarin, the first human to journey into space. With two-thirds of its surface covered in water, Earth is a planet that exuberates its blue radiance in the dark space. However, today, the scarcity of water is a challenge that planet Earth is confronted with. For some, this may be hard to understand. What happened to our blue planet Earth? To put in numbers, more than 97% of the water on Earth consists of seawater, with another 2% locked in ice caps. That only leaves a mere 1% of water available for our daily use. The problem lies in the fact that this 1% of water is gradually becoming scarcer due to reasons such as climate change, environmental pollution, and population growth, leading to increased water stress. 'Water stress' is quantified by the proportion of water demand to the available water resources on an annual basis, indicating the severity of water scarcity as the stress index rises. Higher stress indexes signify experiencing severe water scarcity.

The semiconductor ecosystem, unsustainable without water
Because water stress issues transcend national boundaries, various stakeholders including international organizations and governments work to negotiate water resource management strategies and promote collaboration. UN designates March 22nd as an annual "World Water Day" to raise awareness about the severity of water scarcity running various campaigns. Now, it's imperative for companies to also take responsibility for the water resources given and pursue sustainable management.

According to Bloomberg's latest investigation, Huawei and Semiconductor Manufacturing International Corporation (SMIC) have submitted patents on the self-aligned quadruple patterning (SAQP) pattern etching technique to enable SMIC to achieve 5 nm semiconductor production. The two Chinese giants have been working with the Deep Ultra Violet (DUV) machinery to develop a pattern etching technique allowing SMIC to produce a node compliant with the US exporting rules while maintaining the density improvements from the previously announced 7 nm node. In the 7 nm process, SMIC most likely used self-aligned dual patterning (SADP) with DUV tools, but for the increased density of the 5 nm node, a doubling to SAQP is required. In semiconductor manufacturing, lithography tools take multiple turns to etch the design of the silicon wafer.

Especially with smaller nodes getting ever-increasing density requirements, it is becoming challenging to etch sub-10 nm designs using DUV tools. That is where Extreme Ultra Violet (EUV) tools from ASML come into play. With EUV, the wavelengths of the lithography printers are 14 times smaller than DUV, at only 13.5 nm, compared to 193 nm of ArF immersion DUV systems. This means that without EUV, SMIC has to look into alternatives like SAQP to increase the density of its nodes and, as a result, include more complications and possibly lower yields. As an example, Intel tried to use SAQP in its first 10 nm nodes to reduce reliance on EUV, which resulted in a series of delays and complications, eventually pushing Intel into EUV. While Huawei and SMIC may develop a more efficient solution for SAQP, the use of EUV is imminent as the regular DUV can not keep up with the increasing density of semiconductor nodes. Given that ASML can't ship its EUV machinery to China, Huawei is supposedly developing its own EUV machines, but will likely take a few more years to show.

During its 55th annual shareholders' meeting, Samsung Electronics announced its entry into the AI processor market with the upcoming launch of its Mach-1 AI accelerator chips in early 2025. The South Korean tech giant revealed its plans to compete with established players like NVIDIA in the rapidly growing AI hardware sector. The Mach-1 generation of chips is an application-specific integrated circuit (ASIC) design equipped with LPDDR memory that is envisioned to excel in edge computing applications. While Samsung does not aim to directly rival NVIDIA's ultra-high-end AI solutions like the H100, B100, or B200, the company's strategy focuses on carving out a niche in the market by offering unique features and performance enhancements at the edge, where low power and efficient computing is what matters the most.

According to SeDaily, the Mach-1 chips boast a groundbreaking feature that significantly reduces memory bandwidth requirements for inference to approximately 0.125x compared to existing designs, which is an 87.5% reduction. This innovation could give Samsung a competitive edge in terms of efficiency and cost-effectiveness. As the demand for AI-powered devices and services continues to soar, Samsung's foray into the AI chip market is expected to intensify competition and drive innovation in the industry. While NVIDIA currently holds a dominant position, Samsung's cutting-edge technology and access to advanced semiconductor manufacturing nodes could make it a formidable contender. The Mach-1 has been field-verified on an FPGA, while the final design is currently going through a physical design for SoC, which includes placement, routing, and other layout optimizations.

The Biden-Harris Administration announced today that Intel and the U.S. Department of Commerce have signed a non-binding preliminary memorandum of terms (PMT) for up to $8.5 billion in direct funding to Intel for commercial semiconductor projects under the CHIPS and Science Act. CHIPS Act funding aims to increase U.S. semiconductor manufacturing and research and development capabilities, especially in leading-edge semiconductors. Intel is the only American company that both designs and manufactures leading-edge logic chips. The proposed funding would help advance Intel's critical semiconductor manufacturing and research and development projects at its sites in Arizona, New Mexico, Ohio and Oregon, where the company develops and produces many of the world's most advanced chips and semiconductor packaging technologies.

"Today is a defining moment for the U.S. and Intel as we work to power the next great chapter of American semiconductor innovation," said Intel CEO Pat Gelsinger. "AI is supercharging the digital revolution and everything digital needs semiconductors. CHIPS Act support will help to ensure that Intel and the U.S. stay at the forefront of the AI era as we build a resilient and sustainable semiconductor supply chain to power our nation's future."

Arizona State University (ASU) and Deca Technologies (Deca), a premier provider of advanced wafer- and panel-level packaging technology, today announced a groundbreaking collaboration to create North America's first fan-out wafer-level packaging (FOWLP) research and development center.

The new Center for Advanced Wafer-Level Packaging Applications and Development is set to catalyze innovation in the United States, expanding domestic semiconductor manufacturing capabilities and driving advancements in cutting-edge fields such as artificial intelligence, machine learning, automotive electronics and high-performance computing.

According to the latest report by Reuters, the US government is preparing to announce a multi-billion dollar grant for Intel's chip manufacturing operations in Arizona next week, possibly worth more than $10 billion. US President Joe Biden and Commerce Secretary Gina Raimondo will make the announcement, which is part of the 2022 CHIPS and Science Act aimed at expanding US chip production and reducing dependence on China and Taiwan manufacturing. The exact amount of the grant has yet to be confirmed, but rumors suggest it could exceed $10 billion, making it the most significant award yet under the CHIPS Act. The funding will include grants and loans to bolster Intel's competitive position and support the company's US semiconductor manufacturing expansion plans. This comes as a surprise just a day after the Pentagon reportedly refused to invest $2.5 billion in Intel as a part of a secret defense grant.

Intel has been investing significantly in its US expansion, recently opening a $3.5 billion advanced packaging facility in New Mexico, supposed to create extravagant packaging technology like Foveros and EMIB. The chipmaker is also expanding its semiconductor manufacturing capacity in Arizona, with plans to build new fabs in the state. Arizona is quickly becoming a significant hub for semiconductor manufacturing in the United States. In addition to Intel's expansion, Taiwan Semiconductor Manufacturing Company (TSMC) is also building new fabs in the state, attracting supply partners to the region. CHIPS Act has a total funding capacity of $39 billion allocated for semiconductor production and $11 billion for research and development. The Intel grant will likely cover the production part, as Team Blue has been reshaping its business units with the Intel Product and Intel Foundry segments.

Intel CEO Pat Gelsinger, speaking at the Intel Foundry Services (IFS) Direct Connect event, confirmed to Tom's Hardware that he hopes to turn IFS into the West's premier foundry company, and a direct technological and volume rival to TSMC. He said that there is a clear line of distinction between Intel Products and Intel Foundry, and that later this year, IFS will be more legally distinct from Intel, becoming its own entity. The only way Gelsinger sees IFS being competitive to TSMC, is by making its most advanced semiconductor manufacturing nodes and 3D chip packaging innovations available to foundry customers other than itself (Intel Products), even if it means providing them to companies that directly compete with Intel products, such as AMD and Qualcomm.

Paul Alcorn of Tom's Hardware asked CEO Gelsinger "Intel will now offer its process nodes to some of its competitors, and there may be situations wherein your product teams are competing directly with competitors that are enabled by your crown jewels. How do you plan to navigate those types of situations and maybe soothe ruffled feathers on your product teams?" To this, Gelsinger responded "Well, if you go back to the picture I showed today, Paul, there are Intel products and Intel foundry, There's a clean line between those, and as I said on the last earnings call, we'll have a setup separate legal entity for Intel foundry this year," Gelsinger responded. "We'll start posting separate financials associated with that going forward. And the foundry team's objective is simple: Fill. The. Fabs. Deliver to the broadest set of customers on the planet."

The U.S. Department of Commerce today announced $1.5 billion in planned direct funding for GlobalFoundries (Nasdaq: GFS) (GF) as part of the U.S. CHIPS and Science Act. This investment will enable GF to expand and create new manufacturing capacity and capabilities to securely produce more essential chips for automotive, IoT, aerospace, defense, and other vital markets.

New York-headquartered GF, celebrating its 15th year of operations, is the only U.S.-based pure play foundry with a global manufacturing footprint including facilities in the U.S., Europe, and Singapore. GF is the first semiconductor pure play foundry to receive a major award (over $1.5 billion) from the CHIPS and Science Act, designed to strengthen American semiconductor manufacturing, supply chains and national security. The proposed funding will support three GF projects:

Dylan Patel, of SemiAnalysis, has highlighted worrying industry trends from an October 2021 published report—the Center for Security and Emerging Technology (CSET) document explored and "(outlined) infrastructure investments and regulatory reforms that could make the United States a more attractive place to build new chipmaking capacity and ensure continued U.S. access to key inputs for semiconductor manufacturing." Citing CSET/World Fab Forecast findings, Patel expressed his dissatisfaction with the apparent lack of progress in the region: "The United States is the slowest relevant country in the world to build a fab thanks to NIMBY assholes and the garbage regulatory/permitting system." The SemiAnalysis staffer likely believes that unsuitable conditions remain in place, and continue to hinder any forward momentum—for greenfield fabrications projects, at least.

The CSET 2021 report posited that the proposed $52 billion CHIPS Act fund would not solve all USA chip industry problems—throwing a large sum of money into the pot is not always a surefire solution: "The United States' ability to expeditiously construct fabs has declined at the same time as the total number of fab projects in the United States has declined. Some of this is due to changes in the global semiconductor value chain, which has concentrated resources in Asia as foundries have risen in prominence, and countries like Taiwan, South Korea, and China have established significant market share in the industry from 1990 to 2020. However, during this same 30-year period, the time required to build a new fab in the United States increased 38 percent, rising from an average of 665 days (1.8 years) during the 1990 to 2000 time period to 918 days (2.5 years) during the 2010-2020 time period (Figure 2). At the same time, the total number of new fab projects in the United States was halved, decreasing from 55 greenfield fab projects in the 1990-2000 time period to 22 greenfield fab projects between 2010 and 2020." Intel's work-in-progress Ohio fabrication site has suffered numerous setbacks (including delayed CHIPS Act payments)—the latest news articles suggest that an opening ceremony could occur in late 2026 or early 2027. Reportedly, TSMC's Arizona facility is a frequently runs into bureaucratic and logistical headaches—putting pressure on company leadership at their Hsinchu (Taiwan) headquarters.

Intel is aiming to get its $20 billion fabrication location—in New Albany, Ohio—up and running by 2025, but the advanced manufacturing facility is facing another round of setbacks. According to a WCMH NBC4 local news report (covering the Colombus, Ohio area), a planned "oversized equipment" reshuffle has been delayed—the shifting of heavy machinery was supposed to start last weekend. Extreme weather conditions (flooding) have been cited as major factor, as well as the complicated nature of transporting "overweight and oversized" loads to Team Blue's 1000-acre site. Workers are set to resume efforts this weekend—starting no later than February 17. Tom's Hardware has kept tabs on the Ohio fab's progress: "The project to move the equipment is expected to last over nine months, meaning this phase of Intel's construction could be done near the end of 2024. There isn't a firm indication of how much work remains to be done at the site after the equipment is delivered." TPU previously covered the leading-edge location's indefinitely postponed groundbreaking ceremony—CHIPS Act subsidies were not delivered in an expected timely manner back in 2022.

A couple of media outlets (Tom's Hardware, Network World, etc.) have received an official statement regarding the slippage of events in New Albany: "While we will not meet the aggressive 2025 production goal that we anticipated when we first announced the selection of Ohio in January, 2022, construction has been underway since breaking ground in late 2022 and our construction has been proceeding on schedule. Typical construction timelines for semiconductor manufacturing facilities are 3-5 years from groundbreaking, depending on a range of factors...We remain fully committed to the project and are continuing to make progress on the construction of the factory and supporting facilities this year. As we said in our January 2022 site-selection announcement, the scope and pace of Intel's expansion in Ohio may depend on various conditions." Industry insiders believe that an "opening ceremony" could occur around late 2026, or even early 2027.

Japanese tech giant Canon hopes to shake up the semiconductor manufacturing industry by shipping new low-cost nanoimprint lithography (NIL) machines as early as this year. The technology, which stamps chip designs onto silicon wafers rather than using more complex light-based etching like market leader ASML's systems, could allow Canon to undercut rivals and democratize leading-edge chip production. "We would like to start shipping this year or next year...while the market is hot. It is a very unique technology that will enable cutting-edge chips to be made simply and at a low cost," said Hiroaki Takeishi, head of Canon's industrial group overseeing nanoimprint lithography technological advancement. Nanoimprint machines target a semiconductor node width of 5 nanometers, aiming to reach 2 nm eventually. Takeishi said the technology has primarily resolved previous defect rate issues, but success will depend on convincing customers that integration into existing fabrication plants is worthwhile.

There is skepticism about Canon's ability to significantly disrupt the market led by ASML's expensive but sophisticated extreme ultraviolet (EUV) lithography tools. However, if nanoimprint can increase yields to nearly 90% at lower costs, it could carve out a niche, especially with EUV supply struggling to meet surging demand. Canon's NIL machines are supposedly 40% the cost of ASML machinery, while operating with up to 90% lower power draw. Initially focusing on 3D NAND memory chips rather than complex processors, Canon must contend with export controls limiting sales to China. But with few options left, Takeishi said Canon will "pay careful attention" to sanctions risks. If successfully deployed commercially after 15+ years in development, Canon's nanoimprint technology could shift the competitive landscape by enabling new players to manufacture leading-edge semiconductors at dramatically lower costs. But it remains to be seen whether the new machines' defect rates, integration challenges, and geopolitical headwinds will allow Canon to disrupt the chipmaking giants it aims to compete with significantly.

Global semiconductor capacity is expected to increase 6.4% in 2024 to top the 30 million *wafers per month (wpm) mark for the first time after rising 5.5% to 29.6 wpm in 2023, SEMI announced today in its latest quarterly World Fab Forecast report.

The 2024 growth will be driven by capacity increases in leading-edge logic and foundry, applications including generative AI and high-performance computing (HPC), and the recovery in end-demand for chips. The capacity expansion slowed in 2023 due to softening semiconductor market demand and the resulting inventory correction.

Dai Nippon Printing Co., Ltd. (DNP) has successfully developed a photomask manufacturing process capable of accommodating the 3-nanometer (10-9 meter) lithography process that supports Extreme Ultra-Violet (EUV) lithography, the cutting-edge process for semiconductor manufacturing.

Background
DNP has continually responded to the demands of semiconductor manufacturers in terms of performance and quality. In 2016, we became the world's first merchant photomask manufacturer to introduce the multi-beam mask writing tool (MBMW). In 2020, we developed a photomask manufacturing process for 5 nm EUV lithography processes, and have been supplying masks that meet the needs of the semiconductor market. In this latest development, in order to meet the needs of further miniaturization, we have developed a photomask for EUV lithography capable of supporting 3 nm processes.