TCL CSOT announced it has started moving production equipment into its t8 factory in Guangzhou, China. Feng Zhang, Senior Vice President of TCL CSOT said "The move-in of the first piece of core production equipment marks the t8 project's transition to the equipment installation and commissioning phase". The fab is an 8.6-generation inkjet-printed OLED production line, with mass production scheduled for Q4 2027. Construction started on September 16, 2025, and in less than a year (226 days), the main factory structure was completed. The project has a total investment of approximately RMB 29.5 billion (around $4.42 billion).

When completed, TCL CSOT's t8 fab will process around 22,500 glass substrates monthly. Each substrate measures 2,290 x 2,620 mm, the kind used for manufacturing medium to large-sized OLED panels. For the start, production will focus on displays for tablets, notebooks, and monitors. Also, TCL CSOT explores inkjet-printed OLED technology potential for flexible and foldable panels.

Diamond Foundry Inc. today announced a major milestone in the history of materials technology: the creation of the first-ever D200mm single-crystal diamond, measuring 200 millimeters in diameter. The achievement marks a fundamental step forward in humanity's ability to manufacture diamond as a technology material at semiconductor-relevant scale.

Diamond has long been recognized as an extraordinary material for technology. It combines the highest thermal conductivity with exceptional mechanical strength, electrical insulation, optical properties, and the potential for extreme electronic performance. Yet its use in advanced technology has been constrained by one basic limitation: size. Diamond Foundry's D200mm breakthrough changes that.

The SEMI Silicon Manufacturers Group (SMG) reported today, in its quarterly analysis of the silicon wafer industry, that worldwide silicon wafer shipments increased 13.4% year-on-year to 3,756 million square inches (MSI) from the 3,313 MSI recorded during the same quarter of 2025. Shipments increased 5.1% quarter-over-quarter from the 3,573 MSI recorded during the second quarter of 2026.

"Silicon wafer shipments increased in the third quarter, supported by strong AI-related demand and improving industrial demand," said Masatsugu Miura, Chairman of SEMI SMG and General Manager of Sales & Marketing Department of Sales & Marketing Division at SUMCO Corporation. "AI-related demand continued to broaden beyond advanced logic and memory to include power devices and photonics. Industrial demand strengthened, supported by robotics, AI server power supplies and improving demand for general-purpose industrial semiconductors. Bonding and advanced packaging applications also continued to support demand for 300 mm polished wafers."

Intel is moving some manufacturing capacity away from consumer chips to keep up with demand for its Xeon server processors. During its Q3 2026 earnings call, the company said it will convert some Intel 18A resources at its Oregon facilities to Intel 3, the node behind Xeon 6 "Granite Rapids." According to CFO Dave Zinsner, those 18A wafers "are generally going to build Panther Lake products." Zinsner also indicated that weaker PC demand gives Intel room to make the switch, as the company expects the PC slowdown to last at least through the first half of next year. CEO Lip-Bu Tan said the added Intel 3 capacity should be in production in the second half of 2027.

Intel CEO Lip-Bu TanThe industry continues to navigate one of the most significant supply shortages in the history, driven by the unprecedented demand for Super Intelligence. Against this backdrop, I am pleased by the progress we made growing our server supply in Q3. I'm mindful about the ongoing challenges we face in the future quarters to keep pace with the server demand.

NVIDIA today announced plans with a group of supply chain partners to expand global manufacturing capacity to meet growing demand for its accelerated computing and full-stack AI factory platform.

Working with Amkor Technology, IBIDEN, King Yuan Electronics (KYEC), Samsung Electro-Mechanics, Siliconware Precision Industries (SPIL) and Unimicron Technology Corporation, NVIDIA is enabling new and existing suppliers to expand critical manufacturing capabilities across substrates, advanced packaging, testing and optical engines, strengthening the resiliency and redundancy of NVIDIA's global supply chain.

A Reddit user in the r/watercooling subreddit bought an AMD Ryzen 9 9950X3D2 Dual Edition from Amazon and noticed that something was off. This was his second 9950X3D2 chip, and both chips were sold and shipped by Amazon and arrived in sealed retail boxes, with identical markings on the heat spreader. Flip them over, however, and the newer one looks nothing like the first. It has a large empty area in the middle packed with tiny capacitors, while a genuine AM5 Ryzen chip has gold contact pads covering nearly its entire underside. The user initially assumed AMD had quietly revised the design. Commenters thought otherwise, and the top reply suggests that someone delidded a real 9950X3D2, attached its heat spreader to an old Intel processor, and sent the fake back to Amazon for a refund. That chip has now ended up in our Redditor's hands.

In this case, the layout is a big giveaway, since Intel desktop chips place many of their capacitors on the underside of the substrate, whereas AMD keeps them on top to leave room for contacts. The lettering on the fake also looks smudged, possibly from the delid or a reprint. It's still unclear which Intel CPU sits underneath, and there's no word from Amazon so far on the matter. That's a costly mistake too, considering the 9950X3D2 launched at $899. Amazon has been here before, apparently, with reports of a fake Ryzen 7 9800X3D that turned out to be a 2011-era FX-4100 with a sticker on top. Buyers are advised to record unboxings of expensive parts and, in the case of CPUs, closely inspect both sides of the chip.

Intel has been granted a US patent for a chip package with tiny LEDs built into it, according to a TrendForce report. Titled "IC Package with Micro LEDs" (patent 12,733,303), it describes a semiconductor die with a micro LED attached, embedded at least partially into a glass substrate. Through-glass vias (TGVs) supply power to the LED and connect to the package substrate. The LEDs can apparently use nanowire structures to emit red, green, and blue light. The patent lists a few uses, including illuminated lettering on the CPU surface, personalization for DIY electronics (think RGB lighting), and indicators for electrical testing inside the package. The patent was filed in 2022 but has now been disclosed by Intel.

Of course, most CPUs sit under a heatsink, so it's hard to think of a scenario where glowing letters on a CPU package would make sense. The optical angle is more interesting. It looks like the patent doesn't describe a working optical link, but AU Optronics is developing a Micro LED co-packaged optics module for links of up to 10 meters in AI data centers, and there are rumors of Intel and AUO collaborating. We don't know if anything has been agreed yet. Intel reportedly stepped back from in-house glass substrate R&D last year, then moved to license the tech to others, and in January it showed a glass core substrate with EMIB at NEPCON Japan. Companies file patents all the time, and most never become products, so I wouldn't expect RGB CPUs anytime soon.

TrendForce's latest research into advanced semiconductor packaging reveals that GPU suppliers and hyperscale CSPs are continuing to develop increasingly powerful and versatile AI chips, making larger package sizes a key development priority for 2.5D packaging. Although TSMC's CoWoS-L faces competition from Intel's EMIB-T, its advantages in technology maturity and yield are expected to keep it the mainstream packaging solution for AI chips through 2028.

TrendForce notes that strong AI demand continues to support NVIDIA's push toward integrated GB/VR rack-scale solutions, which incorporate large numbers of chips. NVIDIA's high-end GPU shipments are expected to grow approximately 30% YoY in 2026. AMD, meanwhile, is aggressively promoting its MI400/MI450 series beginning in the second half of 2026, providing further momentum to overall shipments.

LG Display, the world's leading innovator of display technologies, announced today that it has successfully developed a dream OLED patterning method that is free from the conventional fine metal mask (FMM) process, using its own proprietary technology. Its groundbreaking FMM-less method delivers much greater flexibility in mass production as well as brighter panels with longer lifespan and lower power consumption.

The company will unveil FLiPP (FMM-Less innovative Pixel Patterning) for the first time in the world at the International Meeting on Information Display (IMID) 2026 in Busan, where LG Display will host a dedicated exhibition hall for three days from Aug. 19.

The SEMI Silicon Manufacturers Group (SMG) reported today, in its quarterly analysis of the silicon wafer industry, that worldwide silicon wafer shipments increased 7.4% year-on-year to 3,573 million square inches (MSI) from the 3,327 MSI recorded during the same quarter of 2025. Shipments increased 9.1% quarter-over-quarter from the 3,275 MSI recorded during the first quarter of 2026.

"Silicon wafer shipments maintained steady growth in the second quarter, driven by strong and increasing AI-related demand beyond advanced logic and memory to include power devices, photonics, and other markets," said Ginji Yada, Chairman of SEMI SMG and Managing Executive Officer, General Manager, Sales and Marketing Division at SUMCO Corporation. "In addition, industrial and automotive demand is recovering, while memory price pressures are contributing to constrained PC and smartphone demand. Device manufacturers are investing heavily in capacity expansion, and silicon wafer demand growth is expected to continue."

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD330-4: Standard Package High Bandwidth Memory (SPHBM4). SPHBM4 uses the same DRAM dies as HBM4, commonly used in artificial intelligence accelerators, with a new interface base die that enables mounting on standard organic substrates rather than silicon substrates. JESD330-4 is available for download from the JEDEC website.

JESD330-4 SPHBM is architected to operate at the same aggregate data throughput as HBM4 using fewer pins by operating at a higher frequency. Where the HBM4 interface has 2048 data signals, when published, SPHBM4 will define 512 data signals with 4:1 serialization to achieve the same bandwidth. This change allows the relaxed bump pitch required for connection to organic substrates.

LG Innotek, renowned for its optical solution business and leadership in high-performance camera modules, is quickly establishing itself as a key player in package solutions, including high-value-added semiconductor substrates.

Backed by a combination of structural growth drivers—including the rollout of 5G networks, trend toward higher-performing components in premium smartphones, ongoing recovery of the memory market, and rapid expansion of AI and big data applications—the increase in global demand for high-value-added semiconductor substrate products is accelerating.

LG Innotek (CEO Moon Hyuksoo) announced on May 27 that it will participate in the 2026 Electronic Components and Technology Conference (ECTC) to showcase its next-generation semiconductor package substrate technologies to global semiconductor companies. Now in its 76th year, ECTC is the world's largest international conference on semiconductor packaging technologies, organized by the Institute of Electrical and Electronics Engineers (IEEE) in the United States. This year's event will be held over four days from May 26 to 29 (local time) in Orlando, Florida.

It will bring together around 2,000 industry professionals from 20 countries and 135 leading global semiconductor companies, including Intel, Amkor, ASE, and IBM, to share the latest trends in semiconductor packaging technologies.

Breakthrough in chip manufacturing: As part of the European APECS pilot line, researchers at Fraunhofer Institute for Photonic Microsystems IPMS have developed a method that allows different chip components to be fused almost seamlessly into a single unit. By precisely embedding small chiplets into specially structured silicon pockets, Fraunhofer IPMS succeeded in combining the advantages of a compact single chip with the flexibility of modular systems for the first time. This achievement demonstrates the feasibility of quasi-monolithic integration (QMI) and bridges the gap between traditional chip packaging and cutting-edge semiconductor manufacturing.

Growing demands for greater complexity, computing power and system compactness are calling for a radical rethink of semiconductor manufacturing. The vision for future-proof microelectronics is to create systems that are as powerful as a single chip yet offer the flexibility of modular building blocks. Within the APECS pilot line, which focuses on "Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems", Fraunhofer IPMS is pursuing the quasi-monolithic integration (QMI) approach. The aim is to integrate various chip components, such as control electronics, sensors and microelectromechanical systems (MEMS), at the wafer level, while retaining the benefits of a compact single chip.

Global semiconductor materials market revenue increased 6.8% year-over-year to $73.2 billion in 2025, SEMI, reported today in its Materials Market Data Subscription (MMDS). Growth was supported by gains in both the wafer fab materials and packaging materials segments, reflecting higher process complexity, advanced-node demand, and continued investment in high-performance computing and high-bandwidth memory manufacturing.

Wafer fabrication materials revenue increased 5.4% to $45.8 billion. Lithography-related materials, including photomask, photoresist and ancillaries, along with wet chemicals, posted strong double-digit growth as higher process intensity and tighter lithography requirements continued to increase materials consumption.

SK hynix is collaborating with Intel to utilize its Embedded Multi-die Interconnect Bridge (EMIB) 2.5D packaging technology for HBM memory. As SK hynix aims to diversify its supply chain and customers are increasingly considering Intel Foundry, the South Korean memory giant is exploring research and development efforts with Intel on 2.5D packaging technology. Intel's premier 2.5D packaging technology is its EMIB, which interconnects multiple silicon dies using bridges embedded in a packaging substrate. SK hynix is interested in integrating this technology into its HBM memory, presumably to bring its HBM4 memory modules up to standard for EMIB integration, should its AI chip partners choose Intel Foundry for advanced packaging of their next-generation solutions.

We have already covered that small silicon EMIB bridges—available in variants like EMIB-M with embedded MIM capacitors and EMIB-T with TSVs—provide low-cost, high-density shoreline connections ideal for logic-to-logic and logic-to-HBM interfaces. However, until now, SK hynix has been using TSMC and its CoWoS 2.5D packaging technology. As CoWoS is gradually reaching its limits and customers are seeking alternative packaging methods, EMIB is emerging as a strong candidate to continue the scaling of chiplets in many directions beyond the traditional reticle limit of 830 mm² of silicon area.

The SEMI Silicon Manufacturers Group (SMG) reported today, in its quarterly analysis of the silicon wafer industry, that worldwide silicon wafer shipments increased 13.1% year-on-year to 3,275 million square inches (MSI) from the 2,896 MSI recorded during the same quarter of 2025. Sequentially, shipments declined 4.7% quarter-over-quarter from the 3,437 MSI recorded during the fourth quarter of 2025 in line with typical seasonality.

"Silicon wafer demand related to AI data centers continues to be strong, including advanced logic and memory, and also now extending to power management devices," said Ginji Yada, Chairman of SEMI SMG and Managing Executive Officer, General Manager, Sales and Marketing Division at SUMCO Corporation. "Overall, silicon wafer demand has improved, but the recovery is not uniform. Many device companies have noted improvements in the industrial semiconductor segment, and this is creating a more broad-based recovery as wafer inventory is absorbed. Weaker smartphone and PC shipments in the first quarter of this year may show the impact of tighter supply of memory due to AI high bandwidth memory (HBM) allocation decisions."

Kyocera Corporation (President: Shiro Sakushima; "Kyocera") today announced that it is commercializing a new multilayer ceramic core substrate for advanced semiconductor packages, such as xPUs and switch ASICs, which are rapidly scaling in complexity as AI data center architectures evolve. The new product will be unveiled at ECTC 2026, an international conference on semiconductor packaging technologies, in Orlando, Florida, USA, May 26-29, 2026.

Built from Kyocera's proprietary Fine Ceramic materials, the new core substrate is engineered for high-density wiring and exceptional rigidity. According to the company, these characteristics dramatically reduce deformation (warpage) in high-performance semiconductor packages, a key challenge as demand for greater device integration and higher processing speed continues to rise.

TSMC (TWSE: 2330, NYSE: TSM) today debuted its latest innovation in its most advanced process technology at the Company's 2026 North America Technology Symposium. TSMC's new A13 process is a direct shrink of its industry-leading A14 node announced in 2025, enabling even more compact and efficient designs to address insatiable customer demand in computational requirements for next-generation artificial intelligence, high performance computing (HPC), and mobile applications.

Representing TSMC's commitment to continuous improvement, A13 provides 6% area savings from A14. Design rules are fully backward compatible with A14, enabling customers to quickly migrate their designs to TSMC's latest nanosheet transistor technology. In addition, A13 delivers increased power efficiency and performance gains through design-technology co-optimization, and is scheduled to enter production in 2029, one year after A14.

NVIDIA is reportedly experiencing manufacturing issues with its next-generation "Rubin Ultra" GPU design, one of the company's most ambitious chip development projects, due to the limitations of modern packaging technology. The world's largest company is already shipping customer samples of the standard "Rubin" GPUs, with mass shipments set to begin this summer. However, the current roadmap for the upgraded "Rubin Ultra" design may be encountering technological limitations, as NVIDIA's design goals are too ambitious for TSMC's packaging capabilities. Reportedly, NVIDIA plans to double the regular "Rubin" two-die package with 8 HBM4 modules into a new "Rubin Ultra" package that will include four silicon dies and 16 HBM4E modules in a single package. This configuration is scheduled for 2027, but the sheer volume of silicon may be too much for TSMC's packaging, according to Global Semi Research.

In a typical CoWoS package, TSMC usually combines multiple smaller dies and multiple HBM memory modules into a unified package that supports the entire AI build-out. However, with the ambitious "Rubin Ultra" design, NVIDIA planned to use CoWoS-L, which was expected to handle the design and concept that "Rubin Ultra" was based on. It is rumored, however, that in a 2+2 die package—meaning four dies as in this architecture—TSMC is encountering warping issues. The package—which includes a substrate—is bending in multiple directions, causing the compute dies of "Rubin Ultra" to not make complete contact with the underlying substrate. This instability means that TSMC has to explore alternatives within its packaging portfolio. One of these alternatives is a panelized approach called CoPoS, which stands for Chip-on-Panel-on-Substrate.

Intel is accelerating its advanced packaging push with a major move in Malaysia. According to reports from The Edge Malaysia, the company's new complex there, part of Project Pelican, is now 99% complete and set for full operations later this year. Malaysian Prime Minister Datuk Seri Anwar Ibrahim confirmed he met with Intel CEO Tan Lip-Bu and executives to review the project progress. The first phase will launch assembly and testing capabilities for advanced packaging, marking a key step in Intel's foundry expansion strategy. The facility is designed to handle die sort, prep, and full production flows across both EMIB (Embedded Multi-die Interconnect Bridge) and Foveros technologies, critical for supporting high-volume chiplet-based designs. As we reported in December last year, Intel values the project at approximately $7 billion and aims to transform Malaysia into a major regional hub for its advanced packaging operations. An additional $200 million investment has already been committed to finish the site.

Intel continues to advance its EMIB packaging approach. Unlike traditional silicon interposers used by NVIDIA in Blackwell, EMIB embeds conductive bridges directly into the substrate. This approach is cheaper, more efficient, and more suited for high-density chips. Intel is now aiming for 120 x 120 mm packages from the current 100 x 100 mm. These larger dies can support up to twelve HBM stacks, compared with eight in current designs. By 2028, Intel plans 120 x 180 mm packages capable of handling twenty-four HBM stacks. The company has also upgraded EMIB-T, its latest version incorporating through-silicon vias (TSV), to support next-gen HBM4 memory, now entering mass production. That is critical as AI chipmakers demand higher bandwidth and tighter integration. However, bigger isn't always easier. Scaling up package size increases warpage risk and yield challenges during manufacturing.

Wolfspeed, Inc. (NYSE: WOLF), a global leader in silicon carbide technology, today announced that its 300 mm silicon carbide (SiC) technology platform could serve as a foundational materials enabler for advanced AI and high-performance computing (HPC) heterogeneous packaging by the end of this decade.

"As AI workloads continue to increase package size, power density, and integration complexity, we believe new materials foundations will be increasingly important to extend advanced packaging roadmaps," said Elif Balkas, Chief Technology Officer at Wolfspeed. "Our 300 mm silicon carbide platform is designed to align SiC's material advantages with industry-standard manufacturing infrastructure and expand the solution space for next-generation AI and HPC packaging architectures."

Samsung is overhauling the power delivery network in its HBM4E memory to tackle what's becoming one of the bigger engineering headaches in next-gen AI chips. This comes just two weeks after the company shipped its first commercial HBM4, already pushing 11.7 Gbps consistently with headroom up to 13 Gbps. As designs move from HBM4 to HBM4E, the number of power bumps grows from 13,682 to 14,457, packed into the same space with thinner, denser wiring. That drives up current density and resistance, causing IR drop (voltage weakens as it travels through the circuits) while the heat generated in the process makes things worse, creating a feedback loop that can affect performance or even cause circuit failure.

To fix this, Samsung segmented the power network. The large centralized MET4 power block on the base die, previously laid out in big honeycomb-like sections near the interposer, has been split into four smaller sections, with upper layers further broken up to reduce congestion and shorten routing paths. According to Samsung, the results were significant, metal circuit defects dropped 97% compared to HBM4, and IR drop improved by 41%, giving the chip more voltage headroom for higher speeds and better reliability.

Today, the NanoIC pilot line, a European initiative coordinated by imec and dedicated to accelerating innovation in chip technologies beyond 2 nm, releases two first-of-a-kind advanced interconnect process design kits (PDKs): a fine-pitch redistribution layer (RDL) and die-to-wafer (D2W) hybrid bonding PDK. These early-access PDKs bring advanced packaging capabilities within reach of universities, start-ups, and industry innovators and mark an important step in enabling high-density, energy-efficient chip-to-chip connectivity.

As the semiconductor industry moves toward ever more complex and heterogeneous system architectures, advanced packaging has become a key enabler in supporting this progress. Instead of merely enclosing individual chips, today's packaging technologies bring multiple dies (chiplets) together into tightly integrated systems where performance, energy efficiency, and bandwidth hinge on how effectively those components can interact. By enabling chiplets to be interconnected at high density, advanced packaging provides the foundation for the next generation of high-performance computing, AI accelerators, and data-intensive applications.

Worldwide silicon wafer shipments in 2025 increased 5.8% to 12,973 million square inches (MSI) while wafer revenue slipped 1.2% to $11.4 billion over the same period, the SEMI Silicon Manufacturers Group (SMG) reported in its year-end analysis of the silicon wafer industry.

2025 marks an inflection year for wafer shipments, with silicon MSI resuming growth supported by strong demand for advanced epitaxial wafers in logic and polished wafers for high-bandwidth memory (HBM), driven by AI applications. Softness in wafer revenue is mostly attributed to the slow momentum in traditional semiconductor applications where the demand and pricing environment are yet to improve.