Introduction

AMD Ryzen 9 9950X3D2 Dual Edition is the company's ultimate AM5 desktop processor, and the first X3D chip to feature 3D V-Cache on both CCDs. Where the original Ryzen 9 9950X3D and 7950X3D had stacked cache on only one of their two chiplets, the 9950X3D2 eliminates that asymmetry, giving each CCD its own 96 MB L3 cache pool. This is a significant evolution that not only boosts gaming performance across all cores, but also promises to eliminate the software-level scheduling complexity that plagued dual-CCD X3D processors since the Ryzen 9 7950X3D. The "Dual Edition" branding reflects the dual 3D V-Cache configuration. It is a 16-core/32-thread processor with 192 MB of L3 cache—96 MB per CCD (32 MB on-die + 64 MB stacked). The 9950X3D2 offers clock speeds of 4.30 GHz base with up to 5.60 GHz boost, and comes with a TDP of 200 W. The default socket power limit (PPT) is 270 W, up from 200 W on the 9950X3D, with higher current limits to match (EDC 250 A, TDC 180 A). AMD recommends a 360 mm liquid cooler for this chip, compared to 240-280 mm for the 9950X3D.



The 9950X3D2 is based on the same Granite Ridge platform as the rest of the Ryzen 9000 series, with two 8-core Zen 5 chiplets on the 4 nm TSMC N4P node, paired with a 6 nm I/O die. The key difference is that both CCDs now feature 3D V-Cache, so there is no longer a "fast CCD" and a "slow CCD" for gaming. AMD's chipset driver still uses Game Bar to park CCD1 cores during gaming, but does it actually matter? We test this specifically in this review.

3D V-Cache technology has been the most impactful hardware-level innovation by AMD in recent times, establishing the company as the maker of the world's fastest processors for PC gaming for several years running. The Ryzen 7 5800X3D matched the gaming performance of the Intel Core i9-12900K despite being based on the older Zen 3 microarchitecture with slower DDR4 memory. The Ryzen 7 7800X3D dominated gaming over Intel's 13th and 14th Gen Raptor Lake. The 9800X3D and 9850X3D extended that lead with Zen 5 and the inverted die stacking that enabled overclocking on X3D processors for the first time. The original 9950X3D brought 3D V-Cache to the 16-core dual-CCD segment, but only one CCD had the extra cache, requiring Game Bar integration for optimal thread scheduling. Now, the 9950X3D2 takes the concept to its logical conclusion: maximum cores, maximum cache, no compromises.

With Zen 5, AMD inverted the way the CCD and 3D V-Cache die (L3D) are stacked. On older X3D processors, the L3D was stacked on top of the CCD, with structural silicon conducting heat from the CPU cores through the stack. With Zen 5, the CCD sits on top, with the L3D below it, connected via through-silicon vias (TSVs). This means the CPU cores directly dissipate heat to the cooling solution over STIM, with no structural silicon in the way, enabling the same thermal and overclocking characteristics as non-X3D models. Previously, dual 3D V-Cache was exclusive to AMD's server-grade EPYC processors. The 9950X3D2 brings this technology to the consumer desktop for the first time.

The AMD Zen 5 microarchitecture involves a comprehensive reworking of nearly all the core components compared to Zen 4, with a particular focus on the number-crunching capabilities. The core comes with a true 512-bit floating point data-path to more effectively execute 512-bit SIMD workloads that use instruction-sets such as AVX-512, VNNI, etc.; when compared to Zen 4, which uses a dual-pumped 256-bit data-path to execute these instruction-sets.

AMD is pricing the Ryzen 9 9950X3D2 Dual Edition at $900, which positions it as the most premium consumer desktop processor on the market. In return, you get the fastest application performance, combined with class-leading gaming performance across all cores without scheduling compromises. The 9950X3D2 is compatible with all Socket AM5 motherboards; support on AMD 600-series chipset motherboards requires a BIOS update, while AMD 800-series chipset motherboards are drop-in compatible with the latest BIOS.

Architecture

Just like the other Ryzen 9000-series processors, the Ryzen 9 9950X3D2 Dual Edition is a chiplet-based processor with two 8-core chiplets, both featuring 3D V-Cache—a first for AMD's desktop lineup. Previous dual-CCD X3D processors, such as the 9950X3D, only had 3D V-Cache on one of the two chiplets. The 9950X3D2 eliminates this asymmetry. This modularity gives AMD finer control over the die size needed to achieve a given core count. Why 8 cores per chiplet? While AMD could technically go higher, smaller dies yield more good chips per wafer, which keeps costs down. At around 80 mm² per chiplet, 8 cores hits a sweet spot between core count and manufacturing economics. It also gives AMD tremendous product flexibility—one single chiplet design can serve the entire lineup, from 6-core (with two cores disabled) to 16-core (two chiplets), instead of needing separate dies for every core count.


The 9000X3D series debuts the second generation of 3D V-Cache technology. In past generations of X3D chips, such as the Zen 3-based 5800X3D and the Zen 4-based 7800X3D, the 64 MB 3D V-Cache die (L3D) was stacked on top of the CPU complex die (CCD), over its central region that has the 32 MB on-die cache, with structural silicon being installed over the two ends of the CCD that have the CPU cores. These pieces of structural silicon would handle the all-important task of transferring heat from the CPU cores to the cooling solution above.


With the second generation of 3D V-Cache technology, AMD has inverted the way the L3D and CCD stack up. The Zen 5 CCD is now stacked on top of the L3D using TSMC's direct copper-to-copper die bonding technology. Heat from the CCD now dissipates to the cooling solution like on regular Ryzen 9000 series processors. The L3D, on the other hand, is now a sort of base tile, spanning the entire area underneath the CCD. Its central region has the 64 MB L3 cache, while the entire tile is peppered with TSVs (through-silicon vias) that connect the CCD above to the fiberglass substrate below. This design change not only vastly improves thermals for the CCD, but also makes it possible for these chips to have the same overclocking capabilities as regular Ryzen 9000 series processors, such as the 9950X.


The AMD Ryzen 9000 series desktop processors, including the 9950X3D2 Dual Edition, 9800X3D, 9850X3D, 9950X3D, 9900X3D, 9950X, 9900X, 9700X, and 9600X, are based on the new Granite Ridge chiplet-based solution. The CPU complex dies (CCDs) are where all the innovation is focussed, as this is where the Zen 5 CPU cores are located. The rest of the processor is made up of the client I/O die (cIOD), which is carried over from the previous generation, so AMD could save on development costs. AMD built the new-generation CCD on the 4 nm TSMC N4P foundry node, an upgrade from the 5 nm TSMC N5 node, with over 22% power improvement, and 6% transistor density improvements. The CCDs are roughly the same size as the Zen 4 CCDs, and fit in nicely with the substrate floor-plan of the Granite Ridge package.

AMD has retained the CPU core counts of its previous generation, the company continues to not be baited into a core-count war with Intel, triggered by its pivot to heterogeneous multicore and tiny E-cores of which it can cram many of into its processors. The Ryzen 9 9950X3D2 Dual Edition sits at the very top of the Ryzen 9000 lineup. It is a 16-core/32-thread chip with two CCDs, both featuring 3D V-Cache—unlike the original 9950X3D which had cache on only one CCD. This makes the 9950X3D2 the first symmetrical dual-CCD X3D processor, eliminating the need for any software-level scheduling workarounds. Below it in the lineup, the 9850X3D is the company's top single CCD gaming part, an 8-core/16-thread chip.

The Zen 5 Core

With the I/O and packaging aspects of Granite Ridge covered by carrying over the cIOD and existing Socket AM5 infrastructure, all of AMD's engineering attention is on the 4 nm CCD, specifically the Zen 5 CPU cores, since there's not much else on the CCD besides them. It's been AMD's endeavor to give consumers single-thread performance improvements in the form of an IPC uplift, with each new generation of Zen. These generational IPC increases range between 10-19%, and with Zen 5, the company wants you to expect roughly 16% better IPC over Zen 4. AMD designed the Zen 5 core to be "forward-facing" with support for instruction sets that will become more relevant with the advent of AI acceleration into the client space. While the Granite Ridge processor itself lacks an NPU and won't accelerate Copilot+, the Zen 5 cores are designed to improve the working experience of AI software developers and researchers, besides machines that use discrete accelerators, since the CPU-end (software end) of the AI stack can benefit from new capabilities on the cores.


With Zen 5, AMD has updated practically all key areas of the CPU core, including the front-end with its branch prediction unit, the various caches within the core, the fetch/decode pipelines, the execution engine, and the load/store. The front-end sees an updated branch prediction unit. This new BP ensures zero-bubble conditional branches to save clock cycles from mispredictions; a large 16 KB L1 BTB, and a larger tagged-geometric length predictor; a larger 52-entry return address stack, compared to 32-entry on Zen 4; a 16-way Op Cache associativity, compared to 12-way on Zen 4, and a 33% increase in Op Cache and dispatch bandwidth. The BP supports up to 3 prediction windows per cycle, compared to 2 on Zen 4. The L2 and tablewalker latency is obscured with the new aggressive fetch unit. The L2 ITLB supports 2,048 entries, compared to just 512 on the Zen 4 core. The L1 instruction cache gets bandwidth and latency improvements, along with two independent instruction fetch streams.


As with every traditional x86 CPU core, there's a split into Integer and Floating Point units. The Integer engine features an 8-wide dispatch/retire/rename queue depth. The integer scheduler has more "symmetry" to simplify pick operations. It features 6 ALUs with 3 multipliers, and 3 branch units; besides 4 AGUs. The AGU scheduler supports 56 entries, and the ALU scheduler 88, compared to 3× 24-entry ALU+AGU combined scheduling, with a 24-entry dedicated ALU scheduler. The physical register file is up to 240/192 entries from 224/126 on Zen 4. The ROB retire queue buffer holds 448 entries, compared to 320 on Zen 4.


The floating point unit is where Zen 5 seems to have a major design focus. Zen 5 is designed to execute AVX-512 instructions over a full 512-bit data-path, compared to Zen 4, which uses a dual-pumped 256-bit data-path. This should significantly speed up AVX-512, VNNI, and other instructions relevant to AI acceleration on the CPU core. The FPU has four execution pipelines with two LS/integer register pipes. It supports two 512-bit loads, one 512-bit store per cycle, and a 2-cycle FADD. There are updates to the FPU's execution window.


The load/store unit sees several improvements to meet the growth in bandwidth requirements of the execution engine. To begin with, the L1 data cache has been enlarged to 48 KB 12-way, up from 32 KB 8-way on Zen 4. Besides this enlargement, there are improvements to the load/store pipes, with a mix of 4 loads and 2 stores per cycle. Its four integer load pipes can pair into FP pipe. The bandwidth to the L2 cache has been improved.


The core's dedicated L2 cache remains 1 MB in size from the previous generation, but AMD says that it has doubled the associativity and bandwidth of this cache over the one Zen 4 comes with. While AMD has retained 32 MB as the standard on-die L3 cache size, which it shares among the 8 cores on the CCD, it has worked to reduce the cache's latency along with tracking up to 320 L3 in-flight misses.

Granite Ridge SoC Features

Depending on the processor model, the chip features one or two CCDs, each with eight Zen 5 cores, 32 MB of L3 cache, an SMU, and an Infinity Fabric interface, with 32 B/cycle read and 16 B/cycle write bandwidth, to the client I/O die (cIOD). The cIOD uses Infinity Fabric to connect all the various SoC components of the processor, the two most important of which are the dual-channel DDR5 memory controllers (160-bit including ECC), and the 28-lane PCI-Express 5.0 root complex.

AMD provides a basic iGPU with Granite Ridge, just like it did with Raphael. This is based on the older RDNA 2 graphics architecture due to reusing the cIOD from Zen 4, and consists of just one workgroup processor (WGP), or just two compute units (CU), worth 128 stream processors. This iGPU talks to a display controller that supports up to four displays; and a multimedia engine that can accelerate decode of H.265 and AV1.

There's also an integrated USB interface, with support for USB 3.2 (up to two 10 Gbps ports), a couple of USB 2.0 ports, and legacy interfaces, including SPI, eSPI, GPIO, I2C, etc. The client I/O die is built on the 6 nm foundry node, as many of these components don't really benefit from the latest 4 nm node. The cIOD of Granite Ridge is carried over from Raphael, with only some microcode updates that give it native support for DDR5-5600 (Ryzen 7000 natively supported DDR5-5200), various overclocking speeds over AMD EXPO, and support for higher DDR5 overclocking memory speeds using a 1:2 divider between the FCLK and MCLK.

AMD X870E, X870, B850, and B840 Chipsets

Along with the Ryzen 9000 Granite Ridge series, AMD introduced their 800 series desktop motherboard chipset family. The processors are placed in the existing Socket AM5, and as such are compatible with any AMD 600-series chipset motherboard with a BIOS update. Helping things along is the fact that nearly every AM5 motherboard comes with USB BIOS Flashback, which should let you blind-flash your BIOS even if you have an "incompatible" processor.

AMD hasn't changed the I/O of its processors, as we detailed on the previous page, but identified the reasons why some of its 600-series chipset models were vastly outselling the others. Market studies showed that enthusiasts are drawn to the top X670E, and the rest of the crowd to the well-rounded B650, with no takers for the X670 and B650E. AMD set out to correct these by shuffling up the feature-sets among its 800-series chipset models, while also using the occasion to standardize a few I/O features, such as USB4, and encouraging its motherboard partners to provide new connectivity options, such as Wi-Fi 7.


The AMD X870E chipset leads the pack in terms of connectivity. It is a dual-chip solution, much like X670E and X670. You are assured PCI-Express Gen 5 for the x16 PEG slot, as well as the CPU-attached NVMe slots; while the chipset puts out up to 16 Gen 4 PCIe lanes. Also, motherboard designers are mandated to provide 40 Gbps USB4 connectivity.

The X870 (non-E) is a lite version of this chipset, and is a single-chip solution, much like B650E. You'll still get PCI-Express Gen 5 x16 for the PEG slot, as well as Gen 5 for the CPU-attached NVMe slots, however the chipset only puts out 8 Gen 4 PCIe lanes for general purpose I/O. Much like X870E, with X870 you are assured of USB4 connectivity.

The B850 is a successor of the B650. It is a single-chip solution just like X870, but here, motherboard vendors are allowed to wire out the PCI-Express x16 PEG slot as Gen 4. The CPU-attached NVMe interfaces, however, should remain Gen 5 capable. Motherboard vendors can still provide Gen 5 x16 PEG if they want to, but it's optional. USB4 isn't mandatory, so a vendor can design an X870 motherboard and simply pull out the USB4 interface to label the board as B850. Like X870E and X870, the B850 chipset supports both CPU and memory overclocking.

Lastly, there's the B840, an entry-level chipset meant to succeed the A620 and A620A. The PCI-Express x16 PEG runs at a primitive Gen 3 speed. The chipset puts out just 8 Gen 3 lanes. There's no CPU overclocking support, only memory. The B840 should hence power the vast majority of entry-level or commercial desktop motherboards.

The latest AMD chipset driver also introduces a new Application Compatibility Database feature that optimizes a handful of older game titles (such as Metro Exodus, Far Cry 6, and Total War: Warhammer III) by reducing the thread pool size for better L3 cache utilization. This works on all AM5 Ryzen 9 processors, not just X3D models.

Socket AM5

Here are a few pictures of Socket AM5, the star-attraction with this platform. This is a land-grid array (LGA) socket with 1,718 pins.


As with every LGA socket, the pins are on the motherboard, whereas the processor package has contacts that interface with those pins, while a retention brace holds the package in place with a locking lever. Installing a processor on AM5 is similar to doing so on any of the dozens of Intel LGA sockets.


On Socket AM4, removing the four mounting screws resulted in the backplate falling off, which meant you needed three hands when installing a cooler, and several vendors also bundled their own backplates. On Socket AM5 the backplate isn't designed to be removed, which makes cooler installation MUCH easier.


The caps for the socket are not identical to the Intel LGA sockets, so you can't reuse them.

Unboxing and Photography

The Ryzen 9 9950X3D2 Dual Edition comes in a square-shaped box, similar to the other Ryzen 9000 series chips. There's no included cooling solution. The box-art is a slight variation on the theme set by the regular Ryzen 9000 series chips, the AMD arrow is now set against a silver backdrop instead of gray. There's clear marking on the front and back faces that the processor features 3D V-Cache technology.


The Ryzen 9000-series looks just like the previous Ryzen 7000-series Socket AM5 processors. While there are some minimal changes to the SMD capacitor layout, these aren't significant in any way.


The AM5 socket retention brace only applies pressure along the two side protrusions of the IHS. Intel sockets have it the same way. Socket AM5 retains cooler compatibility with AM4, so you're spoiled for choice with aftermarket cooling solutions.

Test Setup

• All applications, games, and processors are tested with the drivers and hardware listed below—no performance results were recycled between test systems.
• All games and applications are tested using the same version.
• All games are set to their highest quality setting unless indicated otherwise.

AIDA64 Cache and Memory Performance

In this first test we're looking at the performance offered by the memory subsystem and the processor's L1, L2 and L3 caches. AIDA64 comes with a great benchmark that provides a nice overview of all these performance characteristics.