Four Products, One Generation

AMD is not shipping just one Venice chip. It is shipping four distinct products under the EPYC 9006 banner, each with its own socket, memory type and target workload. This is a bigger spread than any previous EPYC generation, and it reflects AMD's view that the data center has fragmented into workloads that want very different things from a CPU.

Venice 9006 SP7
The flagship. Up to 256 Zen 6c cores or 96 Zen 6 cores, 16 channels of DDR5, 96 lanes of PCIe Gen 6 in single-socket configurations, and both 1P and 2P support. AMD positions it for cloud, HPC, AI host nodes and agentic services. This is the part shipping today.

Venice 9006 SP8
A smaller socket for mainstream servers. Up to 128 Zen 6c cores or 96 Zen 6 cores, 8 memory channels with two DIMMs per channel, and more PCIe lanes than SP7 at 128 per socket. Aimed at enterprise, storage, edge and telco. Available in the first half of 2027.

Venice-X 9006X SP7
The 3D V-Cache part. Up to 96 cores with 1152 MB of total L3 cache, in the same SP7 socket. AMD calls it "the best 3D V-Cache yet," and it is the first X-series part since Genoa-X—there was no Turin-X. Targeted at EDA and technical computing. Available in the second half of 2027.

Verano 9006 LP
The odd one out, and the most interesting. Verano drops DDR5 entirely in favor of 24 channels of LPDDR5X on field-replaceable SOCAMM modules. It is built for AI host nodes, where the CPU's job is to feed GPUs rather than do the work itself. Also second half of 2027.

Venice-X vs its Predecessors

The L3 cache total is unchanged from Genoa-X, but everything around it moved. Clock speed is up by 1.60 GHz, memory bandwidth is up 3.6x, and the cache is now spread over fewer but larger cache slices. AMD describes it as 3x the cache per core compared to a standard 96-core Venice, which carries 384 MB across its eight Zen 6 CCDs.