Capacity: | 512 GB |
---|---|
Variants: | 256 GB 512 GB 1 TB 4 TB |
Overprovisioning: | 35.2 GB / 7.4 % |
Production: | Active |
Released: | Apr 15th, 2020 |
Price at Launch: | 80 USD |
Part Number: | TM8FP9512G0C311 |
Market: | Consumer |
Form Factor: | M.2 2280 (Double-Sided) |
---|---|
Interface: | PCIe 3.0 x4 |
Protocol: | NVMe 1.3 |
Power Draw: | Unknown |
Manufacturer: | Phison |
---|---|
Name: | PS5012-E12S-32 |
Architecture: | ARM 32-bit Cortex-R5 |
Core Count: | Quad-Core |
Frequency: | 667 MHz |
Foundry: | TSMC |
Process: | 12 nm |
Flash Channels: | 8 @ 667 MT/s |
Chip Enables: | 4 |
Controller Features: | DRAM (enabled) |
Manufacturer: | Micron |
---|---|
Name: | B27A FortisFlash |
Part Number: | IA5AG64AIA |
Type: | TLC |
Technology: | 96-layer |
Speed: | 50 MT/s .. 800 MT/s |
Capacity: | 4 chips @ 1 Tbit |
ONFI: | 4.0 |
Topology: | Floating Gate |
Die Size: | 82 mm² (6.2 Gbit/mm²) |
Dies per Chip: | 2 dies @ 512 Gbit |
Planes per Die: | 4 |
Decks per Die: | 2 |
Word Lines: |
106 per NAND String
90.6% Vertical Efficiency |
Read Time (tR): | 88 µs |
Program Time (tProg): | 800 µs |
Block Erase Time (tBERS): | 15 ms |
Die Read Speed: | 727 MB/s |
Die Write Speed: | 80 MB/s |
Endurance: (up to) |
2000 P/E Cycles
(40000 in SLC Mode) |
Page Size: | 16 KB |
Block Size: | 5184 Pages |
Plane Size: | 236 Blocks |
Type: | DDR3L-1866 CL13 |
---|---|
Name: | Kingston D1216ECMDXGJD |
Capacity: |
256 MB
(1x 256 MB) |
Organization: | 2Gx16 |
Sequential Read: | 3,400 MB/s |
---|---|
Sequential Write: | 2,000 MB/s |
Random Read: | 350,000 IOPS |
Random Write: | 300,000 IOPS |
Endurance: | 800 TBW |
Warranty: | 5 Years |
MTBF: | 2.0 Million Hours |
Drive Writes Per Day (DWPD): | 0.9 |
SLC Write Cache: | Yes |
TRIM: | Yes |
---|---|
SMART: | Yes |
Power Loss Protection: | No |
Encryption: |
|
RGB Lighting: | No |
PS5 Compatible: | No |
Drive:This drive also have a variant with a different controller, the Silicon Motion SM2262ENG Controller:2 main cores using Cortex-R5 clocked at 667 MHz with CoXProcessor technology (one additional dual-core) Cortex-R5 clocked at a lower clock for better efficience. The difference between this revision and the E12 revision is that this has a nichel IHS to improve the temperature, a smaller size, smaller node (12nm TSMC FinFET) and this works with less DRAM capacity. |