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Zhitai TiPlus7100 512 GB

512 GB
Capacity
MAP1602A
Controller
TLC
Flash
PCIe 4.0 x4
Interface
M.2 2280
Form Factor
Front
SSD Controller
Controller
NAND Die
NAND Die
The Zhitai TiPlus7100 is a solid-state drive in the M.2 2280 form factor, launched in October 2022. It is available in capacities ranging from 512 GB to 1 TB. This page reports specifications for the 512 GB variant. With the rest of the system, the Zhitai TiPlus7100 interfaces using a PCI-Express 4.0 x4 connection. The SSD controller is the MAP1602A Falcon Lite from MaxioTech, a DRAM cache is not available. Zhitai has installed 128-layer TLC NAND flash on the TiPlus7100, the flash chips are made by YMTC. To improve write speeds, a pseudo-SLC cache is used, so bursts of incoming writes are processed more quickly. Thanks to support for the fast PCI-Express 4.0 interface, performance is excellent. The TiPlus7100 is rated for sequential read speeds of up to 7,000 MB/s and 3,600 MB/s write; random IOPS reach up to 800K for reads and 600K for writes.
The SSD's price at launch is unknown. The warranty length is set to five years, which is an excellent warranty period. Zhitai guarantees an endurance rating of 300 TBW, a typical value for consumer SSDs.

Solid-State-Drive

Capacity: 512 GB
Variants: 512 GB 1 TB
Overprovisioning: 35.2 GB / 7.4 %
Production: Active
Released: Oct 2022
Part Number: Unknown
Market: Consumer

Physical

Form Factor: M.2 2280 (Single-Sided)
Interface: PCIe 4.0 x4
Protocol: NVMe 1.4
Power Draw: Unknown

Controller

Manufacturer: MaxioTech
Name: MAP1602A Falcon Lite
Architecture: ARM 32-bit Cortex-R5
Core Count: Quad-Core
Foundry: TSMC
Process: 12 nm
Flash Channels: 4 @ 2,400 MT/s
Chip Enables: 4
Controller Features: HMB (enabled)

NAND Flash

Manufacturer: YMTC
Name: Xtacking 2.0 (CDT2A)
Type: TLC
Technology: 128-layer
Speed: 1600 MT/s
Capacity: 2 chips @ 2 Tbit
ONFI: 4.1
Topology: Charge Trap
Die Size: 60 mm²
(8.5 Gbit/mm²)
Dies per Chip: 4 dies @ 512 Gbit
Planes per Die: 4
Decks per Die: 2
Word Lines: 141 per NAND String
90.8% Vertical Efficiency
Read Time (tR): 50 µs
Program Time (tProg): 620 µs
Block Erase Time (tBERS): 20 ms
Die Read Speed: 1280 MB/s
Die Write Speed: 70 MB/s
Endurance:
(up to)		 3000 P/E Cycles
Page Size: 16 KB
Block Size: 2304 Pages
Plane Size: 1980 Blocks

DRAM Cache

Type: None
Host-Memory-Buffer (HMB): 64 MB

Performance

Sequential Read: 7,000 MB/s
Sequential Write: 3,600 MB/s
Random Read: 800,000 IOPS
Random Write: 600,000 IOPS
Endurance: 300 TBW
Warranty: 5 Years
Drive Writes Per Day (DWPD): 0.3
SLC Write Cache: Yes

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: No
Encryption:
  • No
RGB Lighting: Unknown
PS5 Compatible: Yes

Same Drive

This section lists other SSDs in our database using the exact same hardware components

Notes

Controller:

This controller features multiples variants:
F1C - Uses NVMe 1.4
F2C - Uses NVMe 1.4
F3C - Uses NVMe 2.0
F3C U - For 4TB SSDs and uses NVMe 2.0

NAND Die:

Read Time (tR): Maximum is 50 µs, typical is lower
Typical Program Time (tPROG): 620 µs
Maximum Program Time (tPROG): Maximum is 910 µs
Block Erase Time (tBERS): Maximum is 20 ms, typical is lower
Array Eficiency of over 92%
YMTC 128L Xtacking 2.0 cell architecture consists of two decks connected through deck-interface buffer layer which is the same process with KIOXIA 112L BiCS 3D NAND structure. Cell size, CSL pitch, and 9-hole VC layouts keep the same design and dimension (horizontal/vertical WL and BL pitches) with previous 64L Xtacking 1.0 cell. Total number of gates is 141 (141T) including selectors and dummy WLs for the TLC operation.
This layout has a 1x 4 Plane layout, each one lineup side by side
May 4th, 2024 21:35 EDT change timezone

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