Thursday, May 19th 2022
AMD "Navi 31" Rumored to Feature 384-bit GDDR6 Memory Interface
AMD has historically thrown brute memory bus width at solving memory-management problems in its graphics architectures, but the Infinity Cache technology launched with RDNA2 proved to be a game changer, as GPUs with narrow 256-bit memory interfaces could compete with NVIDIA's offerings that have 384-bit wide memory interfaces and faster GDDR6X memory types. It looks like the competition between NVIDIA "Ada" and AMD RDNA3 graphics architectures is about to heat up, as rumors are emerging of AMD giving its biggest next-gen ASIC, the "Navi 31," a 384-bit wide memory interface.
This 50 percent increase in memory bus width, runs in concert with two associated rumors—one, that the company will use faster 20 Gbps GDDR6 memory chips; and two, that AMD may increase the size of the on-die Infinity Cache memory. Samsung is already mass-producing 20 Gbps and 24 Gbps GDDR6 memory chips. These are regular GDDR6 memory chips with JEDEC-standard signaling, and not GDDR6X, an exclusive memory type innovated by NVIDIA and Micron Technology, which leverages PAM4 signaling to increase data-rates. A theoretical "Navi 31" with 20 Gbps GDDR6 memory speeds would enjoy 960 GB/s of memory bandwidth, a massive 87.5 percent bandwidth increase over the RX 6900 XT. The on-die Infinity Cache operates at speeds measured in several TB/s. The increased bus width could also signal an increase in memory sizes, with the RX 6950 XT successor featuring at least 24 GB of memory.
Sources:
Greymon55 (Twitter), VideoCardz
This 50 percent increase in memory bus width, runs in concert with two associated rumors—one, that the company will use faster 20 Gbps GDDR6 memory chips; and two, that AMD may increase the size of the on-die Infinity Cache memory. Samsung is already mass-producing 20 Gbps and 24 Gbps GDDR6 memory chips. These are regular GDDR6 memory chips with JEDEC-standard signaling, and not GDDR6X, an exclusive memory type innovated by NVIDIA and Micron Technology, which leverages PAM4 signaling to increase data-rates. A theoretical "Navi 31" with 20 Gbps GDDR6 memory speeds would enjoy 960 GB/s of memory bandwidth, a massive 87.5 percent bandwidth increase over the RX 6900 XT. The on-die Infinity Cache operates at speeds measured in several TB/s. The increased bus width could also signal an increase in memory sizes, with the RX 6950 XT successor featuring at least 24 GB of memory.
22 Comments on AMD "Navi 31" Rumored to Feature 384-bit GDDR6 Memory Interface
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On Linux.
Just imagine if they do dare to attempt another deliberate price hike 2.0 for this next-gen of GPUs (but this time, though, there won't be any extra stimulus checks, etc. for them to bet on receiving to increase sales) and they mass produce cards with super inflated prices. How would the wounded global economy respond to that?
But with cache you can only go to such extend. At some point you need more bandwidth to supply all the available cores fast enough.
But, latest rumors state a single compute CCD with 6 64 bit memory controller/64 MB Infinity cache chiplets on a cheaper nodes. This way they don't have the problem of 2 GPU on a same card like MI250 and they can maximize the compute CCD on the premium node as much as possible.
Can't wait to see how it will end, that will probably be interesting for sure. There was already an association between infinity cache and each 32 bit memory controller in Navi 2X. It really look each block cache the memory attached to the memory controller. A simple way to make it coherent.
They only moved Vega 64 to hBM2 to make power-consumption more manageable on such a high-end card ( because if the Vega 64 had used GTX 1080 Ti width plus memory capacity, it would have had even lower margins/ higher power, all for a card with GTX 1080 performance!)
But with RDNA they finally have comparable memory efficiency / power consumption to Nvidia. So now would be a good time to go back for a second iteration!
That is also one of the drawback of the cache, the hit ratio get lower at higher resolutions and will probably also get lower on much more complex scene where each pixel will require more data to be processed. This is one of the reason RDNA 2 seems to scale less at 4K than Ampere.
The rumors are for a tripling of that cache so that may be enough to get good scaling at 4k.
But there are other benefits than bandwidth saving for the cache. Since it's much faster (in both bandwidth and latency), it help the frequency scaling since each compute units have to wait less to get the data. One of the reason GPU are clocked lower is to try to hide the memory latency as much as possible. else you just get wasted clocks
I'm still rocking the Vega64 and its been running perfectly fine at 1000-1050 on the HBM2 for over 530GB/s bandwidth.
Here at 14Gbps 192-bit bus (same as 2060), it matches the 2060 pretty closely!
They only added Infinity cache to be able to improve power efficiency, plus increase performance
They really benefited, with a 2x performance increase over the old model:
Explain why on RDNA1 with no infinity cache, They require the same bus width to be able to compete where on RDNA 2, a 256 bit GPU by example (6900xt) compete with GPU that have 368 bus width (3090). Same for 6700xt (192 bit) with 3070 (256 bit) etc..
RDNA1 closed that gap with Turing
Once your architectures are matched on memory compression, then it becomes a question of how much extra die space you want to waste with all that cache? And is it cheaper than spending money on custom GDDR6X?
I expect to pay, but I am not paying silly money even with a 384bit bus.
As for GDDR6X vs Infinity Cache, it's really up to cost and power usage. More cost on the silicon or more cost on the board and components. The fact that Nvidia drastically increase the cache on Lovelace is probably a good hint that just pushing the memory like crazy (with large bus and high power consumption) isn't the best approach.