Friday, September 29th 2023
AMD Zen 5 Microarchitecture Referenced in Leaked Slides
A couple of slides from AMD's internal presentation were leaked to the web by Moore's Law is Dead, referencing what's allegedly the next-generation "Zen 5" microarchitecture. Internally, the performance variant of the "Zen 5" core is referred to as "Nirvana," and the CCD chiplet (CPU core die) based on "Nirvana" cores, is codenamed "Eldora." These CCDs will make up either the company's Ryzen "Granite Ridge" desktop processors, or EPYC "Turin" server processors. The cores themselves could also be part of the company's next-generation mobile processors, as part of heterogenous CCXs (CPU core complex), next to "Zen 5c" low-power cores.
In broad strokes, AMD describes "Zen 5" as introducing a 10% to 15% IPC increase over the current "Zen 4." The core will feature a larger 48 KB L1D cache, compared to the current 32 KB. As for the core itself, it features an 8-wide dispatch from the micro-op queue, compared to the 6-wide dispatch of "Zen 4." The integer execution stage gets 6 ALUs, compared to the current 4. The floating point unit gets FP-512 capabilities. Perhaps the biggest announcement is that AMD has increased the maximum cores per CCX from 8 to 16. At this point we don't know if it means that "Eldora" CCD will have 16 cores, or whether it means that the cloud-specific CCD with 16 "Zen 5c" cores will have 16 cores within a single CCX, rather than spread across two CCXs with smaller L3 caches. AMD is leveraging the TSMC 4 nm EUV node for "Eldora," the mobile processor based on "Zen 5" could be based on the more advanced TSMC 3 nm EUV node.
The opening slide also provides a fascinating way AMD describes its CPU core architectures. According to this, "Zen 3" and "Zen 5" are new cores, while "Zen 4" and the future "Zen 6" cores are leveraged cores. If you recall, "Zen 3" had provided a massive 19% IPC uplift over "Zen 2," which helped AMD dominate the CPU market. Although with a more conservative 15% IPC gain estimate over "Zen 4," the "Zen 5" core is expected to have as big of an impact on AMD's competitiveness.
Speaking of the "Zen 6" microarchitecture and the "Morpheus" core, AMD is anticipating a 10% IPC increase over "Zen 5," new FP16 capabilities for the core, and a 32-core CCX (maximum core-count). This would see a second round of significant increases in CPU core counts.
Diving deep into the "Zen 5" core, and we see AMD introduce an even more advanced branch prediction unit. If you recall, branch predictor improvements had the largest contribution toward the generational IPC gain of "Zen 4." The new branch predictor comes with zero bubble conditional branches capabilities, accuracy improvements, and a larger BTB (branch target buffer). As we mentioned, the core has a larger 48 KB L1D cache, and an unspecified larger D-TLB. There are throughput improvement across the front-end and load/store stages, with dual basic block fetch units, 8-wide op dispatch/rename; Op Fusion, a 50% increase in ALCs, a deeper execution window, a more capable prefetcher, and updates to the CPU core ISA and security. The dedicated L2 cache per core remains 1 MB in size.
Sources:
cyperalien (Reddit), Moore's Law is Dead (YouTube)
In broad strokes, AMD describes "Zen 5" as introducing a 10% to 15% IPC increase over the current "Zen 4." The core will feature a larger 48 KB L1D cache, compared to the current 32 KB. As for the core itself, it features an 8-wide dispatch from the micro-op queue, compared to the 6-wide dispatch of "Zen 4." The integer execution stage gets 6 ALUs, compared to the current 4. The floating point unit gets FP-512 capabilities. Perhaps the biggest announcement is that AMD has increased the maximum cores per CCX from 8 to 16. At this point we don't know if it means that "Eldora" CCD will have 16 cores, or whether it means that the cloud-specific CCD with 16 "Zen 5c" cores will have 16 cores within a single CCX, rather than spread across two CCXs with smaller L3 caches. AMD is leveraging the TSMC 4 nm EUV node for "Eldora," the mobile processor based on "Zen 5" could be based on the more advanced TSMC 3 nm EUV node.
Speaking of the "Zen 6" microarchitecture and the "Morpheus" core, AMD is anticipating a 10% IPC increase over "Zen 5," new FP16 capabilities for the core, and a 32-core CCX (maximum core-count). This would see a second round of significant increases in CPU core counts.
Diving deep into the "Zen 5" core, and we see AMD introduce an even more advanced branch prediction unit. If you recall, branch predictor improvements had the largest contribution toward the generational IPC gain of "Zen 4." The new branch predictor comes with zero bubble conditional branches capabilities, accuracy improvements, and a larger BTB (branch target buffer). As we mentioned, the core has a larger 48 KB L1D cache, and an unspecified larger D-TLB. There are throughput improvement across the front-end and load/store stages, with dual basic block fetch units, 8-wide op dispatch/rename; Op Fusion, a 50% increase in ALCs, a deeper execution window, a more capable prefetcher, and updates to the CPU core ISA and security. The dedicated L2 cache per core remains 1 MB in size.
111 Comments on AMD Zen 5 Microarchitecture Referenced in Leaked Slides
With more IPC per gen, games are getting more demanding for CPUs.
A the 2600K. Once upon a time there was this CPU that could run every game. :)
There were times when you looked at a new hardware release, and you were so amazed that you had to buy straight away. Hardware was also a lot cheaper back then. Those days are over. People (myself included) should learn to buy only when they need to, and not expect every new release to blow our minds. We live in different times, we should adapt.
AMD was initially producing Intel's licensed CPUs due to FABS they had since Intel could not cope with the demand. It was years after 386 and 486 when AMD started producing AMD's own CPU chips.
BTW, if CPU manufacturing is unrelated, why on Earth you bring it up? Zhaoxin uses resources they have in China according to their business idea (replace foreign hardware and software from China and that includes manufacturing)(That is why Taiwan is under pressure from China btw.). Has anyone forced NV to use 8nm Samsung for Ampere? If it is not manufacturing then stop bringing it up as an argument. Even if they did manage the 5nm, I sincerely think that it would still not match Intel nor AMD in performance. Why it is not in the UK US market? well think about, why. I think you can get that one since I have already gave you an idea about it. Zhaoxin is VIA's subsidiary which means Zhaoxin can produce x86 chips using VIA's licensing.
With the Joint Venture, any company that would be willing to take on the CPU market could do it. I don't see any except China (for obvious reasons which I have given you)
From Google: "We cool or we're cool" means we are not enemies, we don't have beef or show hostility toward each other.
I assume this is AM5 CPUs. Maybe I will retire my own 5800x at some point. 15% up from Zen4 and I got zen3 so the uplift will be substantial.
I put my money into my trust of him, and he has been proven correct, and yes, this was clearly before the 7800XT was about to launch, with informed consent I chose to buy the 7900XT then.
Also, having watched his videos of (at the time) the upcoming AMD 7000 series CPU's but not yet trusting him, I decided to keep my 5000 platform and upgrade the CPU, hindsight says that I should really have bought the 7000 platform once the motherboards dropped from their initial highs (being flown in, rather the much cheaper container ships). One could argue that this was a fluke, I obviously cannot say that it wasn't, I will continue to watch and wait, and take in information in all forms from multiple sources before buying into my next platform. Having an open mind, with information from multiple sources is clearly the best option.Do you have a source for this, I have not heard this before (but of course I do not and can not read/watch every bit of information (true of false) out there).