Monday, February 12th 2018
AMD Ryzen "Raven Ridge" Comes with a Limited PCIe Interface
AMD today launched its first desktop Ryzen "Raven Ridge" APUs that combine quad-core "Zen" CPUs with "Vega" based integrated graphics solutions. One of its key specifications that caught our eye is its PCI-Express interface. Apparently, these chips feature just 8 PCI-Express gen 3.0 lanes for discrete graphics, besides 4 lanes dedicated as the chipset-bus, and 4 other lanes driving a 32 Gbps M.2 NVMe slot. What this means for the end-users, is that any discrete graphics cards plugged into the PCI-Express 3.0 x16 slot will run at half the bandwidth - PCI-Express 3.0 x8.
Our various PCI-Express scaling articles, which we regularly redo with the latest high-end GPUs, should tell you that the performance loss between gen 3.0 x16 and gen 3.0 x8 is negligible. This, however, becomes a problem for the small minority of users who combine these processors with AMD X370 chipset motherboards. The second x16 slot (which draws its PCIe lanes by segmenting it from the first x16 slot) won't work, and without at least x8 bandwidth, there's no possibility of NVIDIA SLI functioning, even on X370 motherboards that have SLI certification. One can't even argue that some internal PCIe lane allocation to the iGPU permanently locks 8 lanes away from PEG. AMD confirms that the "Zen" CCX and the "Vega 11" iGPU talk to each other over Infinity Fabric, not PCIe.
AMD responded to our story in advance with this statement:
Our various PCI-Express scaling articles, which we regularly redo with the latest high-end GPUs, should tell you that the performance loss between gen 3.0 x16 and gen 3.0 x8 is negligible. This, however, becomes a problem for the small minority of users who combine these processors with AMD X370 chipset motherboards. The second x16 slot (which draws its PCIe lanes by segmenting it from the first x16 slot) won't work, and without at least x8 bandwidth, there's no possibility of NVIDIA SLI functioning, even on X370 motherboards that have SLI certification. One can't even argue that some internal PCIe lane allocation to the iGPU permanently locks 8 lanes away from PEG. AMD confirms that the "Zen" CCX and the "Vega 11" iGPU talk to each other over Infinity Fabric, not PCIe.
The target market for Raven Ridge, PC builders or DIYers who value the presence of SoC graphics, will select B350 or A320 motherboards, which do not feature the ability to split PCIe lanes. X370 buyers are typically buying the high end Ryzen, such as Ryzen 5 6-core and Ryzen 7 8-core, to go with that class and price motherboard. For the majority of the market, upgrading from the class leading processor graphics inside the Ryzen 5 2400G or Ryzen 3 2200G to a single discrete GPU will be more than enough, given then performance on offer today from discrete graphics cards such as Radeon RX VEGA64 and Radeon RX 580. And today, those buyers can select from our 1st Gen Ryzen desktop processors, including the Ryzen 5 1500X and Ryzen 3 1300X which remain in the product stack for those buyers who value the extra PCIe lanes.
Additionally, we typically expect buyers who want to run mGPU are doing so from day one. These consumers are finding the lure of the of the Threadripper platform very compelling - massive performance, class leading PCIe lanes, and massive memory bandwith are all the perfect complementary features to go with multi-GPU compute, and gaming.
Raven Ridge was created for the ultra thin and light performance notebook segment, but also to scale into the mainstream performance desktop. It does this through the scalability of "Zen" and "Vega" IP, connected by AMDs Infinity Fabric, offering outstanding graphics performance and features for the price point in the desktop market. The scalable nature of the Socket AM4 platform means that there is a path for users to begin with an entry level motherboard and mainstream processor, and now upgrade processor and platform features the same way that people upgrade discrete graphics card.
29 Comments on AMD Ryzen "Raven Ridge" Comes with a Limited PCIe Interface
So, you can install a graphics card (at x8, but that's fine) and a NVMe drive... and 4 lanes "dedicated as the chipset-bus". Not sure what that last part means... but I'm guessing it means it's taking 4 lanes and using that for internal system communications. Are there any lanes available by chipset to install anything else?
16 in total.
4 to USB internal.
4 to PCI-E NVME
8 To gpu.
Chipset can connect other devices like intel platforms.
The reason there hasn't been any uproar around this is quite simple: AMD has never marketed RR as a dGPU gaming platform, nor are they priced or positioned in the market to do this. AMD also has similarly-priced CPU-only alternatives that provide full PCIe connectivity. In other words, AMD is (reasonably clearly) communicating to consumers that RR is for non-dGPU builds, with regular Ryzen being for everyone else. You can add a dGPU, and at 8 lanes of connectivity it will perform within ~98% of a 16-lane connection, but this isn't something AMD focuses on. The selling point here is the best available iGPU. Neither is AMD marketing RR as a high-end platform - the top-end SKU has an MSRP of $169, after all.
Still, AMD either needs to add another 4-8 lanes to their next platform (unlikely to help, as it's still 2+ years out) or incorporate PCIe 3.0 switching in their chipsets. Here, Intel has a huge advantage (even if the x4 DMI link is a potential bottleneck with NVMe and 10GbE). X470 provides 8 PCIe 2.0 lanes, while Z370 provides something like 30 HSIO lanes (the majority of which can be configured as PCIe 3.0, although not above x4 at once, and with a whole bunch of other limitations when it comes to adding networking and other controllers). This is why Intel motherboards can incorporate more m.2 slots than AMD boards, and this is a noticeable advantage for Intel going forward (even if NVMe is still expensive and not really mass-market, this is changing rapidly). This is also, of course, entirely unrelated to RR's PCIe complement, as Zen CPUs have the exact same limitation.