Friday, July 20th 2007
Intel Unveils Itanium 2 9100-Series
Intel has revealed its latest Montvale-based processor line. The new Montvale-based processors (which will replace the current Montecito-based processors) retain the Itanium 2 name, but with a different processor number. Montvale-based processors will carry the 9100-series processor number to differentiate from the Montecito-based 9000-series. The new Itanium 2 9100-series has minor upgrades over the 9000-series such as a faster 667 MHz front-side bus and the demand Based Switching with Enhanced Intel Speedstep Technology that allows the higher-end Itanium 2 9100-series models to enter a low-power state when idle.
Intel will continue to manufacture the Itanium 2 9100-series on a 90nm fabrication process, as with Montecito.
The lowest end Itanium models are the Itanium 2 9120N which runs at a 1.42 GHz clock speed with a 533/400 MHz front-side bus and a 12MB iL3 cache and the Itanium 2 9110N which runs at 1.60 GHz clock speed a 533/400 MHz front-side bus and a 12MB of iL3 cache. It also has
Source:
DailyTech
Intel will continue to manufacture the Itanium 2 9100-series on a 90nm fabrication process, as with Montecito.
16 Comments on Intel Unveils Itanium 2 9100-Series
i.e.... show us the benchies :-)
Get a IA-64 box running 2003 or Vista and show us how "good" these things are... or are not.
If there are any answers like "oh, this type of processor isn't for xyz, its meant for specialist datacentre applications..." etc. then, quite honestly, it's not "TPU" news. :-)
Edit:
Another one, which I hadn't read before now, overviewing IA-64.
floating point. I think....don't quote me on that (I'd really like to see what Dan says...). Ok from wikipedia....I have gained that Itanium is an enterprise sever chip. It has protections against false branch predictions (not so bad of a problem if it happens), it also has the massive cache. It has a super wide pipline, it can execute up to 6 process at once. That's all I've got in ways of advancement of our consumer cpus.CISC > RISC > EPIC.
First of all, chuck out stupid overly complex CISC instructions. Think instruction level parallelism. 128 exposed (non-rename) registers. Lots of execution units and a linearly increasable number thereof. Chuck out branch prediction and allow the compiler to tell the processor exactly what to do. Now unroll all loops, add a lot of cache and get the processor to perform both instructions from a logical op (and use the result that's returned from the parent argument instead of waiting) and you have EPIC. It's a bit more complicated than that but that's the gist of it.
Think of it as SPARC on steroids.
I'm quite interested in Itanium, PowerPC, and misc server related news like this.
But then again, most people like to think my interests are pure fruitzilla fanboi-ism. :wtf:
24Mb L3 cache, baby. HUZZAH!
Now there's the rib! Does Itanium Hardware have AGP or PCI express and do any drivers exist. :-(
www.microsoft.com/servers/64bit/faqs.mspx
www.supermicro.com/products/motherboard/Itanium/E8870/i2DML-8G2.cfm
That, my friend, is a real server.