Synaptics Incorporated (Nasdaq: SYNA) today introduced the xMCU, a new class of microcontrollers that runs multimodal Edge AI, with the launch of the Synaptics Astra SR200 Series. Unlike conventional MCUs constrained by limited on-chip memory and compute, the xMCU combines heterogeneous, AI-native compute and acceleration with integrated high-bandwidth custom DRAM scalable to hundreds of megabytes, enabling larger AI models and richer multimodal workloads to run entirely on-device. The Astra SR200 Series of xMCUs is designed for the next generation of AI wearables, battery-powered sensing devices, connected cameras, streamers, and industrial vision and voice systems.

The SR200 Series is powered by the Synaptics Torq AI engine, which brings a standards-based hardware architecture and unified developer experience featuring the Coral NPU from Google Research. It also comes with the industry's first pairing of the Arm Cortex -M85 and Cortex -M52. Together with integrated vision and audio capabilities and hardware-rooted security, the SR200 Series brings unmatched system design efficiency and cost benefits to Edge and Physical AI designs.

Cadence's AI-driven digital and custom reference flows, tools, and solutions are now certified on Intel 18A-P and Intel 14A technologies, based on the latest Intel Foundry process design kits (PDKs). Building on the companies' recent expansion of design IP optimized for Intel 18A and 18A-P and their multi-year Design Technology Co-Optimization (DTCO) agreement targeting Intel 14A, this new certification provides customers with a signoff-ready path to deploy advanced AI, high performance computing (HPC), and mobile SoCs on Intel Foundry's leading-edge nodes.

Cadence has worked closely with Intel Foundry to co-optimize tools, flows, and methodologies that fully leverage the innovations in Intel 18A, Intel 18A-P, and Intel 14A, including RibbonFET gate-all-around transistors and advanced backside power delivery technologies such as PowerVia and PowerDirect. By tightly coupling process capabilities with Cadence's agentic AI-driven EDA portfolio and high-performance design IP, customers can achieve industry-leading power, performance, and area (PPA) while reducing design risk and time to market.

Cadence (Nasdaq: CDNS) today announced the Cadence Tensilica Hi-fi iQ DSP IP, the sixth generation of its highly successful Hi-fi DSP family, based on a new architecture purpose-built for next-generation voice AI and emerging immersive audio. As these applications proliferate in the home entertainment, automotive infotainment and smartphone markets, the Hi-fi iQ DSP delivers the performance and energy efficiency required to meet growing SoC computational demands. Compared to the industry-leading Tensilica Hi-fi 5s DSP, the Hi-fi iQ DSP offers 2X greater compute performance, 8X higher AI performance and more than 25% energy savings for most workloads—delivering over 40% performance uplift on numerous audio codecs.

"With the increased growth of AI across virtually every facet of the industry, audio and language have become critical interfaces for users," said Anshel Sag, VP and principal analyst, Moor Insights and Strategy. "The AI performance and energy savings with Cadence's new flagship Tensilica Hi-fi iQ DSP position it to enable future AI-enhanced applications and offload processing from other IPs."

Cadence (Nasdaq: CDNS) today announced the industry's first LPDDR5X 9600 Mbps memory IP system solution designed specifically for enterprise and data center applications with high reliability. This innovative solution integrates Cadence's production-proven LPDDR5X IP and Microsoft's advanced redundant array of independent double data rate (RAIDDR) error correction code (ECC) coding schema, delivering a powerful combination of high performance, low power consumption and robust reliability. Microsoft is the first customer to deploy the new system solution.

In the AI infrastructure build-out, LPDDR5X is gaining traction in the data center due to its ability to boost energy efficiency and performance for AI, HPC and other memory-intensive workloads. While LPDDR5X-based systems reduce power consumption and run times, hyperscalers have until now faced a tradeoff between power, performance and area (PPA) and the reliability, availability and serviceability (RAS) offered by DDR5 memory.

Cadence today announced a Chiplet Spec-to-Packaged Parts ecosystem to reduce engineering complexity and accelerate time to market for customers developing chiplets targeting physical AI, data center, and high-performance computing (HPC) applications. Initial IP partners joining Cadence include Arm, Arteris, eMemory, M31 Technology, Silicon Creations and Trilinear Technologies, as well as silicon analytics partner proteanTecs. To help reduce risk and streamline customer adoption, Cadence is collaborating with Samsung Foundry to build out a silicon prototype demonstration of the Cadence Physical AI chiplet platform, including pre-integrated partner IP on the Samsung Foundry SF5A process.

Extending their longstanding history of close collaboration, Cadence and Arm are working together to accelerate innovation across physical and infrastructure AI applications. Cadence will leverage the advanced Arm Zena Compute Subsystem (CSS) and other essential IP to enhance Cadence's Physical AI chiplet platform and Chiplet Framework. The resulting new Cadence solutions accommodate the demanding next-generation edge AI processing requirements for automobiles, robotics and drones, as well as the needs of standards-based I/O and memory chiplets for data center, cloud and HPC applications. The alliances reduce engineering complexities, offer customers a low-risk path to advanced chiplet adoption and pave the way for smarter, safer and more efficient systems.

Delivering the next wave of chiplet innovation, Cadence has successfully taped out its third-generation Universal Chiplet Interconnect Express (UCIe) IP solution, achieving industry-leading 64 Gbps per-lane speeds on the advanced TSMC N3P process. As the industry moves toward increasingly complex AI, high-performance computing (HPC), and data center architectures, the need for robust, high-bandwidth chiplet connectivity has never been greater. This milestone positions Cadence at the forefront of enabling scalable, energy-efficient multi-die systems for the most demanding applications.

As process nodes advance to 3 nm and below, SoC designers face the challenge of balancing optimal power, performance, and area (PPA) with the requirements of high-speed, reliable die-to-die communication. The Cadence UCIe IP solution, fully compliant with the UCIe specification, is engineered to address these challenges directly. Leveraging TSMC's innovative N3P technology, the solution delivers excellent power efficiency, allowing customers to meet aggressive energy budgets without sacrificing performance.

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects that 77 million AI PCs will ship in 2025, representing 31% of the worldwide PC market, and growing to a 55% market share in 2026. Meanwhile, edge AI is multiplying due to a variety of factors, including smaller and more efficient AI algorithms, more powerful AI silicon, and the proliferation of IoT devices.

As laptops, AI PCs, and the latest imaging systems demand even higher performance and lower power, SoCs are challenged to keep pace. Advanced-node SoCs at 5 nm and below must balance efficiency with ultra-low voltages and growing bandwidth needs. High-resolution cameras, faster frame rates, and AI-driven workloads all require interfaces that deliver speed with minimal EMI/RFI noise.

Cadence today announced major advancements in chip design automation and IP, driven by its long-standing relationship with TSMC to develop advanced design infrastructure and accelerate time to market, for AI and HPC customer applications. Cadence and TSMC have collaborated closely across the spectrum from AI-driven EDA to 3D-ICs to IP and photonics, enabling the world's most advanced semiconductors.

Cadence and TSMC have worked together on design infrastructure for advanced process nodes, including TSMC N3, N2 and A16, using Cadence Innovus Implementation System, Quantus Extraction Solution and Quantus Field Solver, Tempus Timing Solution and ECO Option, Pegasus Verification System, Liberate Characterization Portfolio, Voltus IC Power Integrity Solution, Genus Synthesis Solution, Virtuoso Studio and Spectre Simulation Platform. Cadence AI design flows for chip and 3D-IC are now available for TSMC's advanced N3, N2 and A16 process technologies, as well as for new features in TSMC 3DFabric. Additionally, Cadence is collaborating with TSMC on EDA flow development for TSMC's A14 process, with its first PDK to be released later this year. Further, several new Cadence IP are now silicon-proven and available for TSMC N3P.

Cadence today announced the tapeout of the industry's first LPDDR6/5X memory IP system solution optimized to operate at 14.4 Gbps, up to 50% faster than the previous generation of LPDDR DRAM. The new Cadence LPDDR6/5X memory IP system solution is a key enabler for scaling up the AI infrastructure to accommodate the memory bandwidth and capacity demands of next-generation AI LLMs, agentic AI and other compute-heavy workloads for various verticals. Multiple engagements are currently underway with leading AI, high-performance computing (HPC) and data center customers.

The Cadence IP for the JEDEC LPDDR6/5X standard consists of an advanced PHY architecture and a high-performance controller designed to maximize power, performance and area (PPA) while supporting both LPDDR6 and LPDDR5X DRAM protocols for optimal flexibility. The solution supports native integration into traditional monolithic SoCs as well as multi-die system architectures by leveraging the Cadence chiplet framework, enabling heterogeneous chiplet integration. The chiplet framework, including the previous LPDDR generation, was successfully taped out in 2024.

Next-generation consumer and automotive audio is becoming increasingly sophisticated, and market drivers such as generative AI-based audio processing, immersive soundscapes, and advanced infotainment in software-defined vehicles demand stepped-up audio DSP performance. However, a single DSP can no longer meet escalating compute needs, while multiple DSPs pose significant programming challenges.

Today, OEMs and SoC vendors must perform all multicore hardware design and software development on their own while facing increased time-to-market pressures. At the same time, programmers are grappling with the complexity of software-based synchronization of shared memory regions and the proper partitioning of tasks across the multicore cluster. This can result in designs falling short of performance expectations.

Cadence today announced an expansion of its collaboration with Samsung Foundry, including a new multi-year IP agreement to broaden Cadence memory and interface IP solutions in Samsung Foundry's SF4X, SF5A and SF2P advanced process nodes. Furthering their ongoing technology collaboration, the companies are leveraging Cadence's AI-driven design solutions and Samsung's advanced SF4X, SF4U and SF2P process nodes to deliver high-performance, low-power solutions for AI data center, automotive—including advanced driver-assistance systems (ADAS)—and next-generation RF connectivity applications.

Cadence's AI-driven design solutions and comprehensive portfolio of IP and silicon solutions enhance designers' productivity and accelerate time to market (TTM) for leading-edge SoCs, chiplets and 3D-ICs on advanced Samsung Foundry processes. "We support a full portfolio of IP, subsystems and chiplets on the Samsung Foundry process nodes, and our latest multi-year IP agreement strengthens our ongoing collaboration," said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. "By combining Cadence's AI-driven design and silicon solutions with Samsung's advanced processes, we're delivering the leading-edge technologies our mutual customers need to innovate and bring their products to market faster."

Cadence today announced the Cadence Tensilica NeuroEdge 130 AI Co-Processor (AICP), a new class of processor designed to complement any neural processing unit (NPU) and enable end-to-end execution of the latest agentic and physical AI networks on advanced automotive, consumer, industrial and mobile SoCs. Based on the proven architecture of the highly successful Tensilica Vision DSP family, the NeuroEdge 130 AICP delivers more than 30% area savings and over 20% savings in dynamic power and energy without impacting performance. It also leverages the same software, AI compilers, libraries and frameworks to deliver faster time to market. Multiple customer engagements are currently underway, and customer interest is strong.

"With the rapid proliferation of AI processing in physical AI applications such as autonomous vehicles, robotics, drones, industrial automation and healthcare, NPUs are assuming a more critical role," said Karl Freund, founder and principal analyst of Cambrian AI Research. "Today, NPUs handle the bulk of the computationally intensive AI/ML workloads, but a large number of non-MAC layers include pre- and post-processing tasks that are better offloaded to specialized processors. However, current CPU, GPU and DSP solutions involve tradeoffs, and the industry needs a low-power, high-performance solution that is optimized for co-processing and allows future proofing for rapidly evolving AI processing needs."

At its annual flagship user event, CadenceLIVE Silicon Valley 2025, Cadence (Nasdaq: CDNS) today announced a major expansion of its Cadence Millennium Enterprise Platform with the introduction of the new Millennium M2000 Supercomputer featuring NVIDIA Blackwell systems, which delivers AI-accelerated simulation at unprecedented speed and scale across engineering and drug design workloads.

The new supercomputer integrates Cadence's industry-leading solvers with NVIDIA HGX B200 systems, NVIDIA RTX PRO 6000 Blackwell Server Edition GPUs and NVIDIA CUDA-X libraries and solver software. This powerful combination delivers dramatic reductions in simulation run times and up to 80X higher performance versus CPU-based systems for electronic design automation (EDA), system design and analysis (SDA), and drug discovery applications. The supercomputer provides a tightly co-optimized hardware-software stack that enables breakthrough performance with up to 20X lower power across multiple disciplines, accelerating the build-out of AI infrastructure, advancing physical AI machine design and pushing the frontiers of drug design.

Cadence today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK). These advancements are being showcased today at Intel Foundry Direct Connect, underscoring Cadence's continued leadership in driving industry innovation for artificial intelligence and machine learning (AI/ML), high-performance computing (HPC) and advanced mobility applications through its strategic partnership with Intel Foundry.

Cadence has collaborated closely with Intel Foundry to design and optimize a comprehensive range of solutions that fully leverage the innovative features of the Intel 18A/18A-P nodes, including RibbonFET Gate-all-around transistors and PowerVia backside power delivery network. With this collaboration, joint customers can achieve exceptional power, performance and area (PPA) efficiencies, accelerating time to market for cutting-edge system-on-chip (SoC) designs.

Cadence today announced it is furthering its longstanding collaboration with TSMC to accelerate time to silicon for 3D-IC and advanced-node technologies through certified design flows, silicon-proven IP and ongoing technology collaboration. As a leading provider of IP for TSMC N2P, N5 and N3 process nodes, Cadence continues to deliver cutting-edge AI-driven design solutions to the TSMC ecosystem for multiple horizontal applications from chiplets and SoCs to advanced packaging and 3D-ICs. The deep collaboration encompasses certified tools and flows for TSMC's N2P and A16 technologies, paves the way for TSMC's A14 and further unlocks 3D-IC possibilities by extending support for TSMC 3DFabric design and packaging. In addition, Cadence and TSMC are extending tool certification for newly announced TSMC N3C technology based on available N3P design solutions.

Cadence is driving innovation in AI chip design with certified tools and optimized IP for TSMC's advanced N2P and A16 process technologies. Reinforcing its memory IP leadership, Cadence offers TSMC9000 pre-silicon-certified DDR5 12.8G IP for N2P. Cadence digital, custom/analog design and thermal analysis solutions are certified for TSMC N2P and A16 technologies. Combined with continued collaboration on AI-driven digital design solutions for N2P, including leveraging large language models (LLMs), these advancements play an important role in improving digital design flows for future process nodes.

Cadence today announced the industry's first DDR5 12.8 Gbps MRDIMM Gen 2 memory IP system solution on the TSMC N3 process. The new solution addresses the need for greater memory bandwidth to accommodate unprecedented AI processing demands in enterprise and data center applications, including AI in the cloud. The Cadence DDR5 MRDIMM IP boasts a new high-performance, scalable and adaptable architecture based on Cadence's proven and highly successful DDR5 and GDDR6 product lines. With multiple engagements underway with leading AI, HPC and data center customers, this IP solution is already demonstrating its early leadership.

The new Cadence DDR5 IP offers a PHY and a high-performance controller as a complete memory subsystem. The design is validated in hardware using the most recently available MRDIMMs (Gen 2), achieving a best-in-class 12.8 Gbps data rate that doubles the bandwidth using current DDR5 6400 Mbps DRAM parts. The DDR5 IP memory subsystem is based on Cadence's silicon-proven, high-performance architecture, ultra-low latency encryption and industry-leading RAS features. The DDR5 MRDIMM Gen 2 IP is designed to enable advanced SoCs and chiplets with flexible floor plan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements.

Cadence today announced that it has entered into a definitive agreement with Arm to acquire Arm's Artisan foundation IP business, consisting of standard cell libraries, memory compilers, and general-purpose I/Os (GPIOs) optimized for advanced process nodes at the leading foundries. The transaction will augment Cadence's expanding design IP offerings, anchored by a leading portfolio of protocol and interface IP, memory interface IP, SerDes IP at the most advanced nodes, and embedded security IP from the pending Secure-IC acquisition.

By increasing its footprint in SoC designs, Cadence is reinforcing its commitment to continuously accelerate customers' time to market and to optimize their cost, power and performance on the world's leading foundry processes. Cadence will acquire the Arm Artisan foundation IP business through an asset purchase agreement with a concurrent technology license agreement, to be signed at closing and subject to any existing rights. As part of the transaction, Cadence will acquire a highly talented and experienced engineering team that is well respected in the industry and can help accelerate development of both related and new IP products.

Is this week even real?! After 3+ years of pouring our hearts into each beat, and a DECADE after launching Crypt of the NecroDancer, we've hit the launch button! Rift of the NecroDancer is Out Now! 3...2...1... LET'S GO! The Rift is fully open for battle! The NecroDancer's back in an all-new rhythm game! Dragged into a strange new world, Cadence must engage in musical combat with monsters surging through the Rift! Face pulse-pounding Rhythm Rifts where every beat is a battle, all set to an original soundtrack by Danny Baranowsky and friends.

What YOU Think
We really wanna know! Come join our Discord for maximum launch hype vibes! We're also on Bluesky now too! We'll also be closely monitoring in-game bug reports. This is just the beginning for Rift, and we're so excited to be on this journey with y'all! You can also hang with us during our livestreams. P.S. The best way to support us is to grab the game during launch week, but if you wanna go the extra mile, we've also released a Supporter Upgrade with a couple cute cosmetics

Cadence today announced that MediaTek has adopted the AI-driven Cadence Virtuoso Studio and Spectre X Simulator on the NVIDIA accelerated computing platform for its 2 nm development. As design size and complexity continue to escalate, advanced-node technology development has become increasingly challenging for SoC providers. To meet the aggressive performance and turnaround time (TAT) requirements for its 2 nm high-speed analog IP, MediaTek is leveraging Cadence's proven custom/analog design solutions, enhanced by AI, to achieve a 30% productivity gain.

"As MediaTek continues to push technology boundaries for 2 nm development, we need a trusted design solution with strong AI-powered tools to achieve our goals," said Ching San Wu, corporate vice president at MediaTek. "Closely collaborating with Cadence, we have adopted the Cadence Virtuoso Studio and Spectre X Simulator, which deliver the performance and accuracy necessary to achieve our tight design turnaround time requirements. Cadence's comprehensive automation features enhance our throughput and efficiency, enabling our designers to be 30% more productive."

The search for a new Chief Executive Officer (CEO) of Intel has begun following Pat Gelsinger's departure on Monday. And it is not exactly an easy role to be filled. The tech giant's board is primarily considering external candidates to lead the company through one of its most challenging periods. Among the potential successors is Lip-Bu Tan, a former Intel board member and semiconductor industry veteran. Tan, who previously served as CEO of Cadence Design, left Intel's board in August 2023 after disagreements with Gelsinger over the company's strategic direction. Despite these past tensions, Intel's board has reportedly recently approached Tan to gauge his interest in the position. The search for new leadership is extremely difficult, considering the requirements and massive problems the new CEO would face.

Coming at a critical moment for Intel, which has experienced significant financial challenges under Gelsinger's tenure, the new CEO would need to get the Foundry business to pick up and maintain a solid product roadmap. The company's revenue dropped to $54 billion in 2023, marking a nearly one-third decline since Gelsinger took the helm in 2021. Analysts project Intel's first annual net loss since 1986 this year, with long-term signs of recovery. Gelsinger's exit, which came after the board presented him with the option to retire or be removed, reflects growing impatience with the pace of his ambitious turnaround strategy. The company has appointed CFO David Zinsner and senior executive Michelle Johnston Holthaus as interim co-CEOs while the search committee works to identify a permanent replacement.

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the industry's first HBM4 Memory Controller IP, extending its market leadership in HBM IP with broad ecosystem support. This new solution supports the advanced feature set of HBM4 devices, and will enable designers to address the demanding memory bandwidth requirements of next-generation AI accelerators and graphics processing units (GPUs).

"With Large Language Models (LLMs) now exceeding a trillion parameters and continuing to grow, overcoming bottlenecks in memory bandwidth and capacity is mission-critical to meeting the real-time performance requirements of AI training and inference," said Neeraj Paliwal, SVP and general manager of Silicon IP, at Rambus. "As the leading silicon IP provider for AI 2.0, we are bringing the industry's first HBM4 Controller IP solution to the market to help our customers unlock breakthrough performance in their state-of-the-art processors and accelerators."

Intel today announced that its lead products on Intel 18A, Panther Lake (AI PC client processor) and Clearwater Forest (server processor), are out of the fab and have powered-on and booted operating systems. These milestones were achieved less than two quarters after tape-out, with both products on track to start production in 2025. The company also announced that the first external customer is expected to tape out on Intel 18A in the first half of next year.

"We are pioneering multiple systems foundry technologies for the AI era and delivering a full stack of innovation that's essential to the next generation of products for Intel and our foundry customers. We are encouraged by our progress and are working closely with customers to bring Intel 18A to market in 2025." -Kevin O'Buckley, Intel senior vice president and general manager of Foundry Services

Intel Corporation today reported second-quarter 2024 financial results. "Our Q2 financial performance was disappointing, even as we hit key product and process technology milestones. Second-half trends are more challenging than we previously expected, and we are leveraging our new operating model to take decisive actions that will improve operating and capital efficiencies while accelerating our IDM 2.0 transformation," said Pat Gelsinger, Intel CEO. "These actions, combined with the launch of Intel 18A next year to regain process technology leadership, will strengthen our position in the market, improve our profitability and create shareholder value."

"Second-quarter results were impacted by gross margin headwinds from the accelerated ramp of our AI PC product, higher than typical charges related to non-core businesses and the impact from unused capacity," said David Zinsner, Intel CFO. "By implementing our spending reductions, we are taking proactive steps to improve our profits and strengthen our balance sheet. We expect these actions to meaningfully improve liquidity and reduce our debt balance while enabling us to make the right investments to drive long-term value for shareholders."

During the European Technology Symposium 2024, TSMC has announced its readiness to manufacture next-generation HBM4 base dies using both 12 nm and 5 nm nodes. This significant development is expected to substantially improve the performance, power consumption, and logic density of HBM4 memory, catering to the demands of high-performance computing (HPC) and artificial intelligence (AI) applications. The shift from a traditional 1024-bit interface to an ultra-wide 2048-bit interface is a key aspect of the new HBM4 standard. This change will enable the integration of more logic and higher performance while reducing power consumption. TSMC's N12FFC+ and N5 processes will be used to produce these base dies, with the N12FFC+ process offering a cost-effective solution for achieving HBM4 performance and the N5 process providing even more logic and lower power consumption at HBM4 speeds.

The company is collaborating with major HBM memory partners, including Micron, Samsung, and SK Hynix, to integrate advanced nodes for HBM4 full-stack integration. TSMC's base die, fabricated using the N12FFC+ process, will be used to install HBM4 memory stacks on a silicon interposer alongside system-on-chips (SoCs). This setup will enable the creation of 12-Hi (48 GB) and 16-Hi (64 GB) stacks with per-stack bandwidth exceeding 2 TB/s. TSMC's collaboration with EDA partners like Cadence, Synopsys, and Ansys ensures the integrity of HBM4 channel signals, thermal accuracy, and electromagnetic interference (EMI) in the new HBM4 base dies. TSMC is also optimizing CoWoS-L and CoWoS-R for HBM4 integration, meaning that massive high-performance chips are already utilizing this technology and getting ready for volume manufacturing.

Quantum computing. Drug discovery. Fusion energy. Scientific computing and physics-based simulations are poised to make giant steps across domains that benefit humanity as advances in accelerated computing and AI drive the world's next big breakthroughs. NVIDIA unveiled at GTC in March the NVIDIA Blackwell platform, which promises generative AI on trillion-parameter large language models (LLMs) at up to 25x less cost and energy consumption than the NVIDIA Hopper architecture.

Blackwell has powerful implications for AI workloads, and its technology capabilities can also help to deliver discoveries across all types of scientific computing applications, including traditional numerical simulation. By reducing energy costs, accelerated computing and AI drive sustainable computing. Many scientific computing applications already benefit. Weather can be simulated at 200x lower cost and with 300x less energy, while digital twin simulations have 65x lower cost and 58x less energy consumption versus traditional CPU-based systems and others.