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Samsung Developing 160-layer 3D NAND Flash Memory

Samsung Electronics is reportedly developing its 7th generation V-NAND memory with ultra-high 3D stacking technology. The first model will feature at least 160 layers, subsequent models will feature more. In early signs of the company not wanting to yield the technological initiative to China's YMTC, the first 160-layer V-NAND by Samsung is slated to come out roughly around the time YMTC's 128-layer 3D NAND flash hits mass production, towards the end of 2020.

At the heart of the ultra-high 3D stack is Samsung's proprietary Double Stack technology. The double-stack technology creates electron holes at two separate times for current to go through circuits. The current-generation single-stack chips creates these holes once throughout the stack per cycle. The 160-layer NAND flash is expected to herald a 67% increase in densities per package over the 96-layer chips in the market. Densities could also be increased by other means such as switching to newer semiconductor fabrication nodes, and PLC (5 bits per cell), which is currently being developed by KIOXIA.

Samsung Introduces Industry's First All-in-One Power ICs Optimized for Wireless Earbuds

Samsung Electronics, a world leader in advanced semiconductor technology, today announced the industry's first all-in-one power management integrated circuits (PMIC), MUA01 and MUB01, optimized for today's True Wireless Stereo (TWS) devices.

Unlike wireless headphones, TWS earbuds have no wire that connects the two earpieces. Without the connecting wires, TWS devices present users with more freedom in movement and range on their day-to-day activities. However, like other mobile devices, long battery life and small form factors are key requirements for these wireless earbuds.
Samsung PMIC Samsung PMIC Samsung PMIC

Kioxia Develops New 3D Semicircular Flash Memory Cell Structure "Twin BiCS FLASH"

Kioxia Corporation today announced the development of the world's first three-dimensional (3D) semicircular split-gate flash memory cell structure "Twin BiCS FLASH" using specially designed semicircular Floating Gate (FG) cells. Twin BiCS FLASH achieves superior program slope and a larger program/erase window at a much smaller cell size compared to conventional circular Charge Trap (CT) cells. These attributes make this new cell design a promising candidate to surpass four bits per cell (QLC) for significantly higher memory density and fewer stacking layers. This technology was announced at the IEEE International Electron Devices Meeting (IEDM) held in San Francisco, CA on December 11th.

3D flash memory technology has achieved high bit density with low cost per bit by increasing the number of cell stacked layers as well as by implementing multilayer stack deposition and high aspect ratio etching. In recent years, as the number of cell layers exceeds 100, managing the trade-offs among etch profile control, size uniformity and productivity is becoming increasingly challenging. To overcome this problem, Kioxia developed a new semicircular cell design by splitting the gate electrode in the conventional circular cell to reduce cell size compared to the conventional circular cell, enabling higher-density memory at a lower number of cell layers.

Toshiba Talks About 5-Bit-per-Cell (PLC) Flash Memory

Toshiba at the Flash Memory Summit announced they've managed to develop a 5-Bit-per-Cell memory solution Based on its BiCS 4 flash memory technologies, the feat was achieved using a modified module of Quad-Level Cell (QLC) memory. This shows the technology is not only feasible, but has room for improvement, since an adapted QLC technology will always be inferior to a natively-developed, Penta-Level Cell (PLC) solution.

To achieve this ability to store one extra bit of information per cell (compared to QLC), a new level of voltage refinement is required: the cell has to be able to change its state according to one of 32 voltage states, which, in turn, have to be read out correctly by the flash memory controller. This reduces the cell's performance and endurance (as does any increase in the number of bits per cell), and will require a number of solutions to mitigate and compensate for this reduced performance. However, density has become an increasing concern from manufacturers, hence the continued development of deeper, more variable voltage states that allow for even more information to be stored in the same silicon area. Higher density means cheaper solutions, but density increased in such a way has known trade-offs that have been much talked about ever since the transition from Single-Level Cell (SLC) up to the (nowadays ubiquitous) QLC.
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