We heard rumblings about Intel considering a stake in Arm earlier this summer—Reuters picked up on the multinational corporation's leadership negotiating with Japan's SoftBank about becoming a potential anchor investor in the latter's initial public offering (IPO) of Arm Holdings plc. Several big players have reportedly been courted as key strategic partners—Arm already counts some of these corporations as major clients and business partners. The looming IPO has an estimated value of around $60 billion and $70 billion. Intel has made their investment public today, as announced this morning by Stuart Pann, Senior Vice President and General Manager of Foundry Services.

Pann elaborated on his company's major strategic decision, during proceedings at the Goldman Sachs Communacopia & Technology Conference: "80% of TSMC wafers have an Arm processor in them...The fact that our organization, the IFS organization, is embracing Arm at this level, investing in Arm, doing partnerships with Arm should give you a signpost that we are absolutely serious about playing this business. Because if you are not working with Arm, you cannot be a foundries provider." Despite competing in several market segements, Intel Foundry Services (IFS) and Arm announced a multi-generation agreement, earlier this year, to enable chip designers to build low-power compute system-on-chips (SoCs) on the former's 18A process. The now tighter relationship appears to be steering Team Blue back to formerly abandoned pastures—Pann stated: "Our focus will be for now, much more on ARM and around RISC-V, because that is where the volumes is at, but expect more to come out in the coming months...For example, we announced something with Arm, we will do more with them, clearly as they expand their base. They have multiple interests in multiple areas, and they have been a superb partner."

OpenHW Group today announced that the industry's most comprehensive Development Kit for an open-source RISC-V MCU is now available to be ordered. The OpenHW CORE-V MCU DevKit includes an open-source printed circuit board (PCB) which integrates OpenHW's CORE-V MCU and various peripherals, a software development kit (SDK) with a full-featured Eclipse-based integrated development environment (IDE), as well as connectivity to Amazon Web Services (AWS) via AWS IoT ExpressLink for secure and reliable connectivity between IoT devices and AWS cloud services.

The comprehensive open-source CORE-V MCU DevKit enables software development for embedded, internet-of-things (IoT), and artificial intelligence (AI)-driven applications. The CORE-V MCU is based on the open-source CV32E40P embedded-class processor, a small, efficient, 32-bit, in-order open-source RISC-V core with a four-stage pipeline that implements the RV32IM[F]C RISC-V instruction extensions.

Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor, NXP Semiconductors, and Qualcomm Technologies, Inc., have come together to jointly invest in a company aimed at advancing the adoption of RISC-V globally by enabling next-generation hardware development.

Formed in Germany, this company will aim to accelerate the commercialization of future products based on the open-source RISC-V architecture. The company will be a single source to enable compatible RISC-V based products, provide reference architectures, and help establish solutions widely used in the industry. Initial application focus will be automotive, but with an eventual expansion to include mobile and IoT.

The escalating challenges in acquiring high-performance x86 servers have prompted Chinese data center companies to accelerate the shift to Arm-based system-on-chips (SoCs). Investment banking firm Bernstein reports that approximately 40% of all Arm-powered servers globally are currently being used in China. While most servers operate on x86 processors from AMD and Intel, there's a growing preference for Arm-based SoCs, especially in the Chinese market. Several global tech giants, including AWS, Ampere, Google, Fujitsu, Microsoft, and Nvidia, have already adopted or developed Arm-powered SoCs. However, Arm-based SoCs are increasingly favorable for Chinese firms, given the difficulty in consistently sourcing Intel's Xeon or AMD's EPYC. Chinese companies like Alibaba, Huawei, and Phytium are pioneering the development of these Arm-based SoCs for client and data center processors.

However, the US government's restrictions present some challenges. Both Huawei and Phytium, blacklisted by the US, cannot access TSMC's cutting-edge process technologies, limiting their ability to produce competitive processors. Although Alibaba's T-Head can leverage TSMC's latest innovations, it can't license Arm's high-performance computing Neoverse V-series CPU cores due to various export control rules. Despite these challenges, many chip designers are considering alternatives such as RISC-V, an unrestricted, rapidly evolving open-source instruction set architecture (ISA) suitable for designing highly customized general-purpose cores for specific workloads. Still, with the backing of influential firms like AWS, Google, Nvidia, Microsoft, Qualcomm, and Samsung, the Armv8 and Armv9 instruction set architectures continue to hold an edge over RISC-V. These companies' support ensures that the software ecosystem remains compatible with their CPUs, which will likely continue to drive the adoption of Arm in the data center space.

BeagleBoard.org, a leading developer of open-source hardware platforms, is thrilled to announce the highly anticipated launch of BeagleV-Ahead, an innovative single board computer (SBC) based on TH1520, a quad core 64-bit RISC-V SoC from T-Head. This groundbreaking open-source SBC brings a new level of accessibility, performance, and flexibility to the rapidly growing RISC-V ecosystem.

BeagleV-Ahead is set to revolutionize the world of embedded systems and empower developers and enthusiasts worldwide. It represents a significant milestone in the democratization of computer architecture and open-source hardware development. Built around the powerful and energy-efficient RISC-V instruction set architecture (ISA), the BeagleV-Ahead SBC offers unparalleled opportunities for developers, hobbyists, and researchers to explore and experiment with RISC-V technology.

When it comes to APIs, OpenGL is something of a classic. According to the Khronos Group, OpenGL is the most widely adopted 2D and 3D graphics API. Since its launch in 1992 it has been used extensively by software developers for PCs and workstations to create high-performance, visually compelling graphics applications for markets such as CAD, content creation, entertainment, game development and virtual reality.

To date, Imagination GPUs have natively supported OpenGL up until Release 3.3 as well as OpenGL ES (the version of OpenGL for embedded systems), Vulkan (a cross-platform graphics API) and OpenCL (an API for parallel programming). However, thanks to the increasing performance of our top-end GPUs, especially with the likes of the DXT-72-2304, they present a competitive offering to the data centre and desktop (DCD) market. Indeed, we have multiple customers - including the likes of Innosilicon - choosing Imagination GPUs for the flexibility an IP solution, their scalability and their ability to offer up to 6 TFLOPS of compute.

A group of researchers in China have used a new approach to AI to create a full RISC-V processor from scratch. The team set out to answer the question of whether an AI could design an entire processor on its own without human intervention. While AI design tools do already exist and are used for complex circuit design and validation today, they are generally limited in use and scope. The key improvements shown in this approach over traditional or AI assisted logic design are the automated capabilities, as well as its speed. The traditional assistive tools for designing circuits still require many hours of manual programming and validation to design a functional circuit. Even for such a simple processor as the one created by the AI, the team claims the design would have taken 1000x as long to be done by humans. The AI was trained by observing specific inputs and outputs of existing CPU designs, with the paper summarizing the approach as such:

(...) a new AI approach, which generates large-scale Boolean function with almost 100% validation accuracy (e.g., > 99.99999999999% as Intel) from only external input-output examples rather than formal programs written by the human. This approach generates the Boolean function represented by a graph structure called Binary Speculation Diagram (BSD), with a theoretical accuracy lower bound by using the Monte Carlo based expansion, and the distance of Boolean functions is used to tackle the intractability.

Shenzhen based Milk-V has been busy announcing some very high performance RISC-V based platforms, and has now added another to a rapidly growing list. The Milk-V Mars is a new hobbiest grade RISC-V SBC that intentionally mimics the footprint and layout of the Raspberry Pi 3 Model B, so much so that existing cases and accessories will fit. The credit-card sized Mars packs a very competent array of features, starting with the StarFive JH7110 SoC. The JH7110 contains four 64-bit SiFive U74 RISC-V cores clocked as high as 1.5 GHz as well as an integrated Imagination Technologies IMG BXE-2-32 graphics engine with support for Vulkan 1.3, OpenGL ES 3.x, OpenCL 3.0, and Android NN HAL. This SoC should be the perfect choice for an SBC in this form factor, as it has proven to be on the similarly sized PINE64 Star64 as well as StarFive's VisionFive 2. Surrounding the SoC is a single LPDDR4 module, configurable at purchase up to 8 GB, the traditional 40-pin GPIO header row, a M.2 E-Key for WiFi/BT expansion, a MIPI display serial interface with 4K30 output and H.264/H.265 4K60 decoding, MIPI camera serial interface, HDMI, a USB-C for 5 V power input, a 3.5 mm audio jack, and finally the rear I/O block which consists of three USB 3.0 Type-A, a single USB 2.0 Type-A, and the RJ-45 for Gigabit Ethernet as well as PoE. Storage is expandable with both eMMC and microSD cards. The last tiny header is for powering a fan, which many R Pi cases opt to include, but is not included with the Mars. Availability of the Milk-V Mars is listed as "Coming Soon" and prices have not yet been announced. However to compete with the other options on the market we hope, and expect, that it does not exceed $75 USD. Unlike the Milk-V Pioneer there hasn't been any word on whether the Mars will be as open-source friendly, but it would behoove them to consider the option for this type of hobbyist oriented device.

Imagination Technologies is bringing seamless visual experiences to cost-sensitive consumer devices with the new IMG CXM GPU range which includes the smallest GPU to support HDR user interfaces natively.

Consumers are looking for visuals on their smart home platforms that are as detailed, smooth, and responsive as the experience they are accustomed to on mobile devices. At the same time, ambitious content providers are aligning the look and feel of their applications' user interfaces with their cinematic content, by integrating advanced features such as 4K and HDR.

Chinese RISC-V developers Milk-V Technology and SOPHGO recently announced their collaborative open source Milk-V Pioneer developer motherboard and workstation based on the SOPHON SG2042 RISC-V server SoC. The SOPHON SG2042 is a 64-core, 2 GHz SoC based on T-Head Semiconductor's XuanTie C920 64-bit processor design which features clusters of one to four cores, each a 12-stage out-of-order multiple issue superscalar pipeline, and a 128-bit vector engine based on the preliminary RISC-V V Extension version 0.7.1. The SG2042 packs in 64+64 KB (I+D) L1 cache per core, 1 MB of L2 cache per core cluster, 64 MB of L3 system cache, a quad-channel DDR4 controller, and 32 lanes of PCI-E Gen 4. The SG2042 contains no integrated graphics solution.

The Milk-V Pioneer incorporates this highly threaded RISC-V SoC with a modular and expandable standard mATX motherboard featuring four DIMM slots with support for up to 128 GB of DDR4, three full-length PCI-E slots wired for Gen 4 x8, two M.2 M-Key PCI-E Gen 3 x4, one M.2 E-Key for PCI-E 3.0 x1 and USB 2.0, eight USB 3.2 10 Gbps ports, five SATA 6 Gbps ports, and a pair of 2.5G Ethernet ports. The bulk of this I/O runs off an ASMedia ASM 2824 PCI-E switch, however the PCI-E Gen 4 ports run directly off the SG2024 SoC. Milk-V Pioneer is also being offered as a prebuilt small form factor workstation which puts the board into a small portable chassis called the Pioneer Box. The Pioneer Box includes 64 GB of DDR4-3200, 1 TB M.2 SSD, an Intel X520-T2 10G network card, an AMD Radeon R5 230 graphics card for display, and a 350 W power supply.

Tenstorrent hosted their "Nerds Talking to Nerds About RISC-V" event this week in India where a dozen high profile industry experts hosted technical talks and panels about every facet of the RISC-V landscape and future. Among these are some familiar names to anyone who's been keeping up on the CPU industry; Raja Koduri of his own AI Generative Gaming startup company, Lars Bergstrom of Google, Naveed Sherwani of Rapid Silicon, and of course Jim Keller the CEO of Tenstorrent itself. On the first day of the event a mere 42 minutes into the YouTube live stream during his keynote talk, Jim Keller is providing an overview of Tenstorrent's latest silicon design goals. He presents a slide showing a wide comparison of various competitor's integer performance in SPEC CPU 2017 INT wherein a raw performance value for AMD's yet released "Zen 5" is listed, as well as the operating frequency and TDP of the supposed sample.

The slide shows all of AMD's recent architectures starting with the original "Zen" (Naples) and the improvements each successive generation has made. Also shown is one of Intel's latest "Sapphire Rapids" Xeons, a projected performance point of NVIDIA's in-house CPU architecture "Grace", Amazon's "Graviton" series with a projected result for "Graviton 3," and Tenstorrent's own 8-wide RISC-V architecture as it currently performs in their labs. While all of these are fascinating results in their own right, we're going to narrow in on the "Zen 4" (Genoa) and "Zen 5" results. We can see from the Frequency and TDP charts that "Zen 4" is clocked at 3.8 GHz as it's equal to the Xeon Platinum 8480+ (which itself boosts to 3.8 GHz in light threaded workloads such as this) so is therefore likely a variant of EPYC 9354 or 9454 with its TDP configured at the minimum 240 W. The unnamed "Zen 5" CPU is shown to be running at around 4.0 GHz with the same 240 W TDP, a tiny 5% bump in core clock, while delivering a substantial 30% jump in performance. The most interesting detail here is that nowhere is it listed—as with "Grace" and "Graviton 3"—that this is a projected result.

ASUS IoT, the global AIoT solution provider, today announced the all-new Tinker V—a versatile single-board computer (SBC) powered by a 64-bit RISC-V-based processor, which supports both Linux Debian and Yocto operating systems. Tinker V packs features rich connectivity into a compact Pico-ITX form factor, and pairs assured longevity with reliable support, making it the ideal choice for diverse IoT and gateway applications.

The RISC-V processor in Tinker V employs the open-source Instruction Set Architecture (ISA), based on Reduced Instruction Set (RISC) principles. Compared with traditional x86 and Arm platforms, the defining benefit of RISC-V is that ISA is open source. Both individual developers and enterprises can change, optimize and deploy freely based on the RISC-V architecture—bypassing licensing and copyright fees.

Think Silicon, the leading provider of ultra-low-power GPU IP for embedded systems, will showcase its latest graphics and AI solutions for edge computing devices in Hall 4, Booth 476 at Embedded World 2023 taking place in Nuremberg, Germany from March 14-16. The solutions demonstrate how Think Silicon is meeting the complex needs of ultra-low-power graphics and AI applications in the wearables, smart home, industrial and automotive markets.

Think Silicon's booth will feature the industry's first RISC-V-based GPU - the NEOX IP Series. NEOX represents a new era of smart GPU architectures with programmable compute shaders, running on a real-time operating system (RTOS) and supported by lightweight graphics and machine learning programming frameworks. NEOX serves as a GPU platform addressing a wide variety of vertical markets, including next-generation ultra-low-power smartwatches, augmented reality (AR) eyewear, surveillance and entertainment video, and smart displays for point-of-sale/point-of-interaction terminals.

Yesterday, Intel reported that the company experienced one of the most challenging quarters and year overall revenue results, which led the company's share price to plummet and erase almost 10 billion dollars from its market cap. Amid the economic downtrend, the company is preparing to axe unnecessary developments and research costs that it would get in low-margin markets. Today, this has been reflected in the company's network switch business and the RISC-V pathfinder program. In 2019, the company acquired Barefoot Networks, which ended up in a line of Tofino series of standalone network switches. Apparently, this has been a low-margin or unprofitable business for Intel. "NEX continues to do well and is a core part of our strategic transformation, but we will end future investments in our network switching product line, while still fully supporting existing products and customers," noted Intel CEO Pat Gelsinger, adding, "Since my return, we have exited seven businesses, providing in excess of $1.5 billion in savings". Intel NICs are not affected, and the company's investments in other networking businesses continue.

Additionally, the company is also doing a shutdown of its RISC-V Pathfinder program. Thanks to Yusuke Ohara, who questioned Intel's Pathfinder for RISC-V program support, we have information that the company is discontinuing the program "effective immediately." The support also advises that Intel will not provide additional advancements or bug fixes, so everyone should consult 3rd parties for any software and development.

Back in February 2022 SiFive announced its partnership with Intel Foundry Services (IFS), to bring its "Horse Creek" SoC to market and now SiFive has announced that it's getting ready to launch its first development board on said SoC. This summer, SiFive will launch the HiFive Pro P550 development board, which will kick things up a serious notch when it comes to embedded SoC development boards, regardless of the CPU core the SoC is built around. The HiFive Pro P550 will be one of few microATX based embedded SoC development boards out there and so far, to our knowledge, the only one with a RISC-V based SoC. The Horse Creek SoC sports quad core, 2.2 GHz, 13-stage, triple-issue, out-of-order pipeline RISC-V RV64GBC CPU built on the Intel 4 node. The SoC also has a DDR5 5600 MHz memory interface, support for eight lanes of PCIe 5.0 and comes in a 19 x 19 mm FBGA package.

The HiFive Pro P550 will offer 16 GB of DDR5 memory, but based on the render of the motherboard, this is soldered to the board, rather than relying on standard DDR5 DIMMs. Furthermore, the board has two x16 PCIe 3.0 expansion slots, although it's unclear how many PCIe each slot features, as well as a PCIe 3.0 M.2 2280 M-key slot for NVMe SSDs and a PCIe 3.0 M.2 E-key slot for a WiFi/Bluetooth module. The board also sports multiple USB/USB 3.0 ports and even a pair of USB-C ports. The press release also mentions both Gigabit and 10 Gbps Ethernet support, as well as support for onboard graphics and remote system management, without going into any further details. It'll be interesting to see if the Horse Creek SoC can deliver on its expected performance target, especially as SiFive has a lot to prove, especially as the company calls the RISC-V architecture inevitable.

Ventana Micro Systems Inc. today announced its Veyron family of high performance RISC-V processors. The Veyron V1 is the first member of the family, and the highest performance RISC-V processor available today. It will be offered in the form of high performance chiplets and IP. Ventana Founder and CEO Balaji Baktha will make the public announcement during his RISC-V Summit keynote today.

The Veyron V1 is the first RISC-V processor to provide single thread performance that is competitive with the latest incumbent processors for Data Center, Automotive, 5G, AI, and Client applications. The Veyron V1 efficient microarchitecture also enables the highest single socket performance among competing architectures.

Phison Electronics Corp., a global leader in NAND flash and storage solutions, announced today that its 8 TB M.2 2280 SSD solution has completed flight qualification tests required for Lonestar Data Holdings' historic first lunar data center mission. This SSD has been selected by Lonestar's contractor and Phison's partner, space logistics company Skycorp. Skycorp is also Lonestar's engineering design and manufacturing partner for the lunar data center mission scheduled for the second half of 2023.

"After comprehensive testing and certification process, Phison is thrilled that our SSD technology has passed all the rigorous requirements for Lonestar's upcoming Moon mission," said K.S. Pua, Phison CEO. "We are excited about playing a vital role on this important mission, and other future ones as we continue our foray into the new frontier. We also want to thank our outstanding customer, Lonestar, and partner, Skycorp, for helping to make this happen."

Today, at Linley Fall Processor Conference 2022, Andes Technology, a leading provider of high efficiency, low power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, reveals its top-of-the-line AndesCore AX60 series of power and area efficient out-of-order 64-bit processors. The family of processors are intended to run heavy-duty OS and applications with compute intensive requirements such as advanced driver-assistance systems (ADAS), artificial intelligence (AI), augmented/virtual reality (AR/VR), datacenter accelerators, 5G infrastructure, high-speed networking, and enterprise storage.

The first member of the AX60 series, the AX65, supports the latest RISC-V architecture extensions such as the scalar cryptography extension and bit manipulation extension. It is a 4-way superscalar with Out-of-Order (OoO) execution in a 13-stage pipeline. It fetches 4 to 8 instructions per cycle guided by highly accurate TAGE branch predictor with loop prediction to ensure fetch efficiency. It then decodes, renames and dispatches up to 4 instructions into 8 execution units, including 4 integer units, 2 full load/store units, and 2 floating-point units. Besides the load/store units, the AX65's aggressive memory subsystem also includes split 2-level TLBs with multiple concurrent table walkers and up to 64 outstanding load/store instructions.

SiFive, Inc. the founder and leader of RISC-V computing, today announced two new products that address the need for high performance and efficiency in a small size in high volume applications like wearables, smart home, industrial automation, AR/VR, and other consumer devices. The SiFive Performance P670 and P470 RISC-V processors bring unparalleled compute performance and efficiency that is significantly raising the bar for innovative designs in these high-volume markets. The modern and innovative SiFive design methodologies bring raw compute density that is a substantial advantage for SiFive Performance products and also translates into significant cost savings for customers.

"The P670 and P470 are specifically designed for, and capable of handling the most demanding workloads for wearables and other advanced consumer applications. These new products offer powerful performance and compute density for companies looking to upgrade from legacy ISAs," said Chris Jones, SiFive VP of Product. "We have optimized these new RISC-V Vector enabled products to deliver the performance and efficiency improvements the industry has long been asking for, and we are in evaluations with a number of top-tier customers. Additionally, as the upstream enablement of RISC-V has started within the Android Open Source Project, (AOSP), designers will have unrivaled choice and flexibility as they consider the positive implications with that platform for future designs."

In December of 2021, we covered the appearance of Russia's home-grown Baikal-S processor, which has 48 cores based on Arm Cortex-A75 cores. Today, thanks to the famous chip photographer Fritzchens Fritz, we have the first die shows that show us exactly how Baikal-S SoC is structured internally and what it is made up of. Manufactured on TSMC's 16 nm process, the Baikal-S BE-S1000 design features 48 Arm Cortex-A75 cores running at a 2.0 GHz base and a 2.5 GHz boost frequency. With a TDP of 120 Watts, the design seems efficient, and the Russian company promises performance comparable to Intel Skylake Xeons or Zen1-based AMD EPYC processors. It also uses a home-grown RISC-V core for management and controlling secure boot sequences.

Below, you can see the die shots taken by Fritzchens Fritz and annotated details by Twitter user Locuza that marked the entire SoC. Besides the core clusters, we see that a slum of cache connects everything, with six 72-bit DDR4-3200 PHYs and memory controllers surrounding everything. This model features a pretty good selection of I/O for a server CPU, as there are five PCIe 4.0 x16 (4x4) interfaces, with three supporting CCIX 1.0. You can check out more pictures below and see the annotations for yourself.

According to Dylan Patel of SemiAnalysis sources, Apple is moving its embedded cores from Arm to RISC-V. In Apple's Silicon designs, there are far more cores than the main ones that power the operating system and end-user applications. For example, embedded cores are present, and there are 30+ in M1 SoCs responsible for all kinds of workloads not related to the operating system. These tasks are usually associated with other functions such as WiFi/BlueTooth, ThunderBolt retiming, touchpad control, NAND chips having their own core, etc. They run their own firmware and power everything around the central cores that run the OS, so the whole SoC functions appropriately.

It appears that a lot of these cores are based on Arm M-series or lower-end A-series IP that Apple is currently looking to replace with RISC-V. Given that a large portion of software runs on the main big.LITTLE configuration, other secondary SoC tasks can migrate to a different ISA like RISC-V, with a small firmware adjustment. Given that these cores can be placed with custom IPs, Apple would save licensing fees if custom RISC-V cores were used. Additionally, developing firmware for these cores at an Apple engineering team size shouldn't be a problem. Of course, we have no information about when these custom cores will appear inside Apple Silicon. Even when they are used, no formal announcement is expected given that the main cores remain to be powered by Arm ISA, with everything else invisible to the end-user.

SiFive, Inc., the founder and leader of RISC-V computing, today announced it has been selected by NASA to provide the core CPU for NASA's next generation High-Performance Spaceflight Computing (HPSC) processor. HPSC is expected to be used in virtually every future space mission, from planetary exploration to lunar and Mars surface missions. HPSC will utilize an 8-core, SiFive Intelligence X280 RISC-V vector core, as well as four additional SiFive RISC-V cores, to deliver 100x the computational capability of today's space computers. This massive increase in computing performance will help usher in new possibilities for a variety of mission elements such as autonomous rovers, vision processing, space flight, guidance systems, communications, and other applications.

"As the leading RISC-V, U.S. based, semiconductor company we are very proud to be selected by the premier world space agency to power their most mission critical applications," said Jack Kang, SVP Business Development, SiFive. "The X280 demonstrates orders of magnitude performance gains over competing processor technology and our SiFive RISC-V IP allows NASA to take advantage of the support, flexibility, and long-term viability of the fast-growing global RISC-V ecosystem. We've always said that with SiFive the future has no limits, and we're excited to see the impact of our innovations extend well beyond our planet."

MIPS, a leading developer of highly scalable RISC processor IP, announced it is working with Intel to accelerate innovation in open computing. As part of this effort, MIPS' eVocore is being incorporated into the new Intel Pathfinder for RISC-V, a platform designed to deliver new capabilities for pre-silicon development. Intel Pathfinder allows new ways for System-on-a-Chip (SoC) architects and system software developers to define new products and pursue pre-silicon software development on RISC-V.

"MIPS is thrilled to be part of the Intel Pathfinder for RISC-V platform, providing high performance cores with support for multi-cluster, multi-core and multi-threading to accelerate innovation," said Desi Banatao, MIPS CEO. "These multiprocessors have unique features and a high level of scalability that make them ideal for compute-intensive tasks across a broad range of markets and applications."

The UEFI Forum today announced the release of the Unified Extensible Firmware Interface (UEFI) 2.10 specification and Advanced Configuration and Power Interface (ACPI) 6.5 specification. The new specification versions expand support for new processor types, memory interfaces and platform types, while allowing for crypto agility in post-quantum system security.

"We are excited to share the new Conformance Profiles feature, responsive to community pull for a way to make the UEFI Forum's work useful," said Mark Doran, UEFI Forum President. "The Conformance Profiles feature will expand the platform types UEFI can support to an ever wider range of platform types like IoT, embedded and automotive spaces - beyond general purpose computers."

DeepComputing and Xcalibyte today opened pre-orders for the industry's first native RISC-V development laptop. The hotly anticipated ROMA development platform features an unannounced quad-core RISC-V processor with a companion NPU/GPU for the fastest, seamless RISC-V native software development available.

"Native RISC-V compile is a major milestone," said Mark Himelstein, Chief Technology Officer for RISC-V International. "The ROMA platform will benefit developers who want to test their software running natively on RISC-V. And it should be easy to transfer code developed on this platform to embedded systems."