AVX-512 was proposed by Intel more than a decade ago—in 2013 to be precise. A decade later, the implementation of this instruction set on CPU cores remains wildly spotty—Intel implemented it first on an HPC accelerator, then its Xeon server processors, then its client processors, before realizing that hardware hasn't caught up with the technology to execute AVX-512 instructions in an energy-efficient manner, before deprecating it on the client. AMD implemented it just a couple of years ago with Zen 4 with a dual-pumped 256-bit FPU on 5 nm, before finally implementing a true 512-bit FPU on 4 nm. AVX-512 is a microcosm of what's wrong with the x86 ecosystem.

There are only two x86 CPU core vendors, the IP owner Intel, and its only surviving licensee capable of contemporary CPU cores, AMD. Any new additions to the ISA introduced by either of the two have to go through the grind of their duopolistic competition before software vendors could assume that there's a uniform install base to implement something new. x86 is a net-loser of this, and Arm is a net-winner. Arm Holdings makes no hardware of its own, except continuously developing the Arm machine architecture, and a first-party set of reference-design CPU cores that any licensee can implement. Arm's great march began with tiny embedded devices, before its explosion into client computing with smartphone SoCs. There are now Arm-based server processors, and the architecture is making inroads to the last market that x86 holds sway over—the PC. Apple's M-series processors compete with all segments of PC processors—right from the 7 W class, to the HEDT/workstation class. Qualcomm entered this space with its Snapdragon Elite family, and now Dell believes NVIDIA will take a swing at client processors in 2025. Then there's RISC-V. Intel finally did something it should have done two decades ago—set up a multi-brand Ecosystem Advisory Group. Here's what it is, and more importantly, what it's not.

Altera, an Intel Company, today unveiled an array of FPGA hardware, software and development tools that make its programmable solutions more accessible across a broader range of use cases and markets. At its annual developer's conference, Altera revealed new details on its next-generation, power- and cost-optimized Agilex 3 FPGAs and announced new development kits and software support for its Agilex 5 FPGAs.

"Working closely with our ecosystem and distribution partners, Altera remains committed to delivering FPGA-based solutions that empower innovators with leading-edge programmable technologies that are easy to design and deploy. With these key announcements, we continue to execute on our vision of shaping the future by using programmable logic to help customers unlock greater value across a broad range of use cases within the data center, aerospace and defense sectors, communications infrastructure, automotive, industrial, test, medical and embedded markets," said Sandra Rivera, CEO of Altera.

Microsoft's Direct3D and HLSL teams have unveiled plans to integrate SPIR-V support into DirectX 12 with the upcoming release of Shader Model 7. This significant transition marks a new era in GPU programmability, as it aims to unify the intermediate representation for graphical-shader stages and compute kernels. SPIR-V, an open standard intermediate representation for graphics and compute shaders, will replace the proprietary DirectX Intermediate Language (DXIL) as the shader interchange format for DirectX 12. The adoption of SPIR-V is expected to ease development processes across multiple GPU runtime environments. By embracing this open standard, Microsoft aims to enhance HLSL's position as the premier language for compiling graphics and compute shaders across various devices and APIs. This transition is part of a multi-year development process, during which Microsoft will work closely with The Khronos Group and the LLVM Project. The company has joined Khronos' SPIR and Vulkan working groups to ensure smooth collaboration and rapid feature adoption.

While the transition will take several years, Microsoft is providing early notice to allow developers and partners to plan accordingly. The company will offer translation tools between SPIR-V and DXIL to facilitate a gradual transition for both application and driver developers. For those not familiar with graphics development, graphics APIs ship with virtual instruction set architectures (ISA) that abstracts standard hardware features at a higher level. As GPUs don't follow the same ISA as CPUs (x86, Arm, RISC-V), this virtual ISA is needed to define some generics in the GPU architecture and allow various APIs like DirectX and Vulkan to run. Instead of focusing support on several formats like DXIL, Microsoft is embracing the open SPIR-V standard, which will become de facto for API developers in the future, allowing focus on more features instead of constantly replicating each other's functions. While DXIL is used mainly for gaming environments, SPIR-V has adoption in high-performance computing as well, with OpenCL and SYCL. Gaming presence is also there with Vulkan API, and we expect to see SPIR-V join DirectX 12 games.

In a notable step forward for the RISC-V architecture, the Box86 and Box64 emulator developers have successfully run The Witcher 3 on a RISC-V processor. While performance is far from optimal, even on a Milk-V Pioneer with a 64-core processor and an AMD Radeon RX 5500 XT graphics card, the achievement is remarkable.

RISC-V, a free and open-source instruction set architecture, is still in its early stages compared to established platforms like ARM and x86/x64. Despite this, the Box86/Box64 team, known for creating environments to run Windows programs on Linux, has demonstrated that AAA gaming is possible on RISC-V hardware. To accomplish this feat, the developers utilized Box64 with Wine and DXVK to emulate the necessary instructions.

Today SiFive, Inc., the gold standard for RISC-V computing, announced its new SiFive Performance P870-D datacenter processor to meet customer requirements for highly parallelizable infrastructure workloads including video streaming, storage, and web appliances. When used in combination with products from the SiFive Intelligence product family, datacenter architects can also build an extremely high-performance, energy efficient compute subsystem for AI-powered applications.

Building on the success of the P870, the P870-D supports the open AMBA CHI protocol so customers have more flexibility to scale the number of clusters. This scalability allows customers to boost performance while minimizing power consumption. By harnessing a standard CHI bus, the P870-D enables SiFive's customers to scale up to 256 cores while harnessing industry-standard protocols, including Compute Express Link (CXL) and CHI chip to chip (C2C), to enable coherent high core count heterogeneous SoCs and chiplet configurations.

Akeana, the company committed to driving dramatic change in semiconductor IP innovation and performance, has announced its official company launch approximately three years after its foundation, having raised over $100 million in capital, with support from A-list investors including Kleiner Perkins, Mayfield, and Fidelity. Today's launch marks the formal availability of the company's expansive line of IP solutions that are uniquely customizable for any workload or application.

Formed by the same team that designed Marvell's ThunderX2 server chips, Akeana offers a variety of IP solutions, including microcontrollers, Android clusters, AI vector cores and subsystems, and compute clusters for networking and data centers. Akeana moves the industry beyond the status quo of legacy vendors and architectures, like Arm, with equitable licensing options and processors that fill and exceed current performance gaps.

DeepComputing partners with Canonical to unveil a huge boost to the DC-ROMA RISC-V Laptop family. The DC-ROMA RISC-V Laptop II is the world's first RISC-V laptop pre-installed and powered by Ubuntu, which is one of the most popular Linux distributions in the world, providing developers with an outstanding mix of usability and reliability, as well as a rich ecosystem with security and support.

Equipped with octa-core 64-bit RISC-V AI CPU
Adding to a long list of firsts, the new DC-ROMA laptop II is the first to feature SpacemiT's SoC K1 - with its 8-cores RISC-V CPU running at up to 2.0 GHz with 16 GB of memory. This significantly doubled its overall performance and energy efficiency over the previous generation's 4-cores SoC running at 1.5 GHz. Moreover, SpacemiT's SoC K1 is also the world's first SoC to support RISC-V high performance computing RVA 22 Profile RVV 1.0 with 256 bit width, and to have powerful AI capabilities with its customised matrix operation instruction based on IME Group design principle!

MIPS, a leading developer of efficient and configurable IP compute cores, will showcase the company's latest innovations and suite of system deployments at Computex 2024. As part of its activities at Computex 2024, MIPS will highlight its latest solutions demonstrating the company's differentiation around data movement to enable customers to achieve Edge AI innovation. MIPS' architecture enables a bespoke solution with tight integration of the CPU to the overall System-on-Chip (SoC) architecture, managing data movement and memory balancing to predict and solve bottlenecks caused by the increasing throughput demands of new use-cases in AI.

"We are excited to participate in Computex 2024 where we will show how we've evolved as a company and are developing RISC-V tools that give edge AI Embedded customers the freedom to innovate compute," said Durgesh Srivastava, CTO of MIPS. "We remain committed to providing our customers and partners with the innovative solutions they need to succeed in today's rapidly evolving accelerated computing markets. We are anticipating a lot of interest in our technology at the show and look forward to connecting with ecosystem partners, our customers and fellow industry leaders."

The open-source RISC-V instruction set architecture is shaping up for explosive growth over the next several years, primarily fueled by the increasing demand for artificial intelligence (AI) across industries. A new forecast from tech research firm Omdia predicts that shipments of RISC-V-based chips will skyrocket at an astonishing 50% annual growth rate between 2024 and 2030, sitting at a staggering 17 billion RISC-V units in 2030. The automotive sector is expected to see the most significant growth in RISC-V adoption, with a forecasted annual increase of 66%. This growth is largely attributed to the unique benefits RISC-V offers in this industry, including its flexibility and customizability.

The rise of AI in the automotive sector, particularly in applications such as autonomous driving and advanced driver assistance systems (ADAS), is also expected to contribute to RISC-V's success. Industrial applications will continue to be the largest domain for RISC-V, accounting for approximately 46% of sales. However, the growth in the automotive sector is expected to outpace other industries, driven by the increasing demand for AI-enabled technologies in this sector. The forecast from Omdia is based on current trends and the growing adoption of RISC-V by major players in the tech industry, including Google and Meta, which are investing in RISC-V to power their custom solutions. Additionally, chip producers like Qualcomm are creating their RISC-V chips for consumer use, further solidifying the technology's future position in the market.

The US government is investigating the potential national security risks associated with China's involvement in the development of open-source RISC-V chip technology. According to a letter obtained by Reuters, the Department of Commerce has informed US lawmakers that it is actively reviewing the implications of China's work in this area. RISC-V, an open instruction set architecture (ISA) created in 2014 at the University of California, Berkeley, offers an alternative to proprietary and licensed ISAs like those developed by Arm. This open-source ISA can be utilized in a wide range of applications, from AI chips and general-purpose CPUs to high-performance computing applications. Major Chinese tech giants, including Alibaba and Huawei, have already embraced RISC-V, positioning it as a new battleground in the ongoing technological rivalry between the United States and China over cutting-edge semiconductor capabilities.

In November, a group of 18 US lawmakers from both chambers of Congress urged the Biden administration to outline its strategy for preventing China from gaining a dominant position in RISC-V technology, expressing concerns about the potential impact on US national and economic security. While acknowledging the need to address potential risks, the Commerce Department noted in its letter that it must proceed cautiously to avoid unintentionally harming American companies actively participating in international RISC-V development groups. Previous attempts to restrict the transfer of 5G technology to China have created obstacles for US firms involved in global standards bodies where China is also a participant, potentially jeopardizing American leadership in the field. As the review process continues, the Commerce Department faces the delicate task of balancing national security interests with the need to maintain the competitiveness of US companies in the rapidly evolving landscape of open-source chip technologies.

Today at Embedded World, SiFive, Inc., the pioneer and leader of RISC-V computing, unveiled its new state-of-the-art RISC-V development board, the HiFive Premier P550. The board will be available for large-scale deployment through Arrow Electronics so developers around the world can test and develop new RISC-V applications like machine vision, video analysis, AI PC and others, allowing them to use AI and other cutting-edge technologies across many different market segments.

With a quad-core SiFive Performance P550 processor, the HiFive Premier P550 is the highest performance RISC-V development board in the industry, and the latest in the popular HiFive family. Designed to meet the computing needs of modern workloads, the out-of-order P550 core delivers superior compute density and performance in an energy-efficient area footprint. Furthermore, the modular design of the HiFive Premier P550, which includes a replaceable system-on-module (SOM) board, gives developers the flexibility they need to tailor their designs.

Imagination Technologies today unveils the next product in the Catapult CPU IP range, the Imagination APXM-6200 CPU: a RISC-V application processor with compelling performance density, seamless security and the artificial intelligence capabilities needed to support the compute and intuitive user experience needs for next generation consumer and industrial devices.

"The number of RISC-V based devices is skyrocketing with over 16Bn units forecast by 2030, and the consumer market is behind much of this growth" says Rich Wawrzyniak, Principal Analyst at SHD Group. "One fifth of all consumer devices will have a RISC-V based CPU by the end of this decade. Imagination is set to be a force in RISC-V with a strategy that prioritises quality and ease of adoption. Products like APXM-6200 are exactly what will help RISC-V achieve the promised success."

While we are all used to having a system with a CPU, GPU, and, recently, NPU—X-Silicon Inc. (XSi), a startup founded by former Silicon Valley veterans—has unveiled an interesting RISC-V processor that can simultaneously handle CPU, GPU, and NPU workloads in a chip. This innovative chip architecture, which will be open-source, aims to provide a flexible and efficient solution for a wide range of applications, including artificial intelligence, virtual reality, automotive systems, and IoT devices. The new microprocessor combines a RISC-V CPU core with vector capabilities and GPU acceleration into a single chip, creating a versatile all-in-one processor. By integrating the functionality of a CPU and GPU into a single core, X-Silicon's design offers several advantages over traditional architectures. The chip utilizes the open-source RISC-V instruction set architecture (ISA) for both CPU and GPU operations, running a single instruction stream. This approach promises lower memory footprint execution and improved efficiency, as there is no need to copy data between separate CPU and GPU memory spaces.

Called the C-GPU architecture, X-Silicon uses RISC-V Vector Core, which has 16 32-bit FPUs and a Scaler ALU for processing regular integers as well as floating point instructions. A unified instruction decoder feeds the cores, which are connected to a thread scheduler, texture unit, rasterizer, clipping engine, neural engine, and pixel processors. All is fed into a frame buffer, which feeds the video engine for video output. The setup of the cores allows the users to program each core individually for HPC, AI, video, or graphics workloads. Without software, there is no usable chip, which prompts X-Silicon to work on OpenGL ES, Vulkan, Mesa, and OpenCL APIs. Additionally, the company plans to release a hardware abstraction layer (HAL) for direct chip programming. According to Jon Peddie Research (JPR), the industry has been seeking an open-standard GPU that is flexible and scalable enough to support various markets. X-Silicon's CPU/GPU hybrid chip aims to address this need by providing manufacturers with a single, open-chip design that can handle any desired workload. The XSi gave no timeline, but it has plans to distribute the IP to OEMs and hyperscalers, so the first silicon is still away.

MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc. to accelerate ecosystem enablement of MIPS RISC-V IP and their customer's ability to innovate compute without constraints. MIPS will showcase MIPS' RISC-V IP Core technology utilizing the Synopsys ImperasFPM Fast Processor Models and the Synopsys ImperasPDK Processor Development Kit software simulation tools at embedded world 2024.

The MIPS RISC-V P8700 IP featured in the demo at embedded world, is a versatile processor, available in scalable multicore configurations, capable of running Linux and other high-level operating systems (HLOS) and is suitable for a variety of automotive (and non-automotive) applications. As a key benefit, customers using the Synopsys ImperasFPM and ImperasPDK fast simulation solution can get started early with software development for the MIPS P8700 and I8500.

InnoGrit's low-wattage 12 nanometer IG5666 controller popped up on the T-FORCE GE PRO PCIe 5.0 SSD series earlier in the year, but attention has turned to another consumer-grade design. Parent company—Yingren Technology—is not well known outside of China, although its InnoGrit brand has started to make inroads within Western markets. The enterprise-level YRS900 PCIe 5.0 SSD controller was announced last September—this open-source RISC-V-based solution was designed/engineered to "align with U.S. export restrictions." According to cnBeta and MyDrivers reports, a new YRS820 controller has successfully reached the mass production phase. This is a PCIe 5.0 consumer-grade controller, likely derived from its big sibling (YRS900).

According to InnoGrit presentation material, their new model is based on: "RISC-V instruction architecture, adopts a 4-channel PCIe 5.0 interface, is equipped with 8 NAND flash memory channels, supports NVMe 2.0 protocol, has an interface transmission rate of 2667MT/s, can be paired with 3D TLC/QLC, and supports a maximum capacity of up to 8 TB." Company representatives stated that the YRS820 controller is destined to be fitted on high-end consumer parts—the AI PC market segment is a key goal, since the YRS820 is able to: "accelerate data processing for specific applications and have high stability, consistency and security." cnBeta highlighted some anticipated performance figures: "YRS820 achieves sequential read 14 GB/s, sequential write 12 GB/s, random read and random write up to 2000K IOPs and 1500K IOPs respectively." InnoGrit did not reveal a release timetable, since their latest consumer-grade controller is going through a validation process. The company is currently collaborating with domestic NAND flash memory and DRAM manufacturers, as well as other industry bodies.

Chinese e-commerce and cloud giant Alibaba announced its plans to launch a server-grade RISC-V processor later this year, and it showcased a RISC-V-powered laptop running an open-source operating system. The announcements were made by Alibaba's research division, the Damo Academy, at the recent Xuantie RISC-V Ecological Conference in Shenzhen. The upcoming server-class processor called the Xuantie C930, is expected to be launched by the end of 2024. While specific details about the chip have not been disclosed, it is anticipated to cater to AI and server workloads. This development is part of Alibaba's ongoing efforts to expand its RISC-V portfolio and reduce reliance on foreign chip technologies amidst US export restrictions. To complement the C930, Alibaba is also preparing a Xuantie 907 matrix processing unit for AI, which could be an IP block inside an SoC like the C930 or an SoC of its own.

In addition to the C930, Alibaba showcased the RuyiBOOK, a laptop powered by the company's existing T-Head C910 processor. The C910, previously designed for edge servers, AI, and telecommunications applications, has been adapted for use in laptops. Strangely, the RuyiBOOK laptop runs on the openEuler operating system, an open-source version of Huawei's EulerOS, which is based on Red Hat Linux. The laptop also features Alibaba's collaboration suite, Ding Talk, and the open-source office software Libre Office, demonstrating its potential to cater to the needs of Chinese knowledge workers and consumers without relying on foreign software. Zhang Jianfeng, president of the Damo Academy, emphasized the increasing demand for new computing power and the potential for RISC-V to enter a period of "application explosion." Alibaba plans to continue investing in RISC-V research and development and fostering collaboration within the industry to promote innovation and growth in the RISC-V ecosystem, lessening reliance on US-sourced technology.

Tenstorrent and MosChip Technologies announced today that they are partnering on design for Tenstorrent's cutting-edge RISC-V solutions. In selecting MosChip Technologies, Tenstorrent stands to strongly advance both its own and its customers' development of RISC-V solutions as they work together on Physical Design, DFT, Verification, and RTL Design services.

"MosChip Technologies is special in that they have unparalleled tape out expertise in design services, with more than 200 multi-million gate ASICs under their belt", said David Bennett, CCO of Tenstorrent. "Partnering with MosChip enables us to design the strongest RISC-V solution we can to serve ourselves, our partners, and our customers alike."

According to the report from a journal called Fundamental Research, researchers from the Institute of Computing Technology at the Chinese Academy of Sciences have developed a 256-core multi-chiplet processor called Zhejiang Big Chip, with plans to scale up to 1,600 cores by utilizing an entire wafer. As transistor density gains slow, alternatives like multi-chiplet architectures become crucial for continued performance growth. The Zhejiang chip combines 16 chiplets, each holding 16 RISC-V cores, interconnected via network-on-chip. This design can theoretically expand to 100 chiplets and 1,600 cores on an advanced 2.5D packaging interposer. While multi-chiplet is common today, using the whole wafer for one system would match Cerebras' breakthrough approach. Built on 22 nm process technology, the researchers cite exascale supercomputing as an ideal application for massively parallel multi-chiplet architectures.

Careful software optimization is required to balance workloads across the system hierarchy. Integrating near-memory processing and 3D stacking could further optimize efficiency. The paper explores lithography and packaging limits, proposing hierarchical chiplet systems as a flexible path to future computing scale. While yield and cooling challenges need further work, the 256-core foundation demonstrates the potential of modular designs as an alternative to monolithic integration. China's focus mirrors multiple initiatives from American giants like AMD and Intel for data center CPUs. But national semiconductor ambitions add urgency to prove domestically designed solutions can rival foreign innovation. Although performance details are unclear, the rapid progress shows promise in mastering modular chip integration. Combined with improving domestic nodes like the 7 nm one from SMIC, China could easily create a viable Exascale system in-house.

Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor ASA, NXP Semiconductors, and Qualcomm Technologies, Inc., have formally established Quintauris GmbH. Headquartered in Munich, Germany, the company aims to advance the adoption of RISC-V globally by enabling next-generation hardware development.

The formation of Quintauris was formally announced in August, with the aim to be a single source to enable compatible RISC-V-based products, provide reference architectures, and help establish solutions to be widely used across various industries. The initial application focus will be automotive, but with an eventual expansion to include mobile and IoT.

Chinese company Sipeed has introduced the Lichee Pocket 4A, one of the first handheld gaming devices based on the RISC-V open-source instruction set architecture (ISA). Sipeed positions the device as a retro gaming platform capable of running simple titles via software rendering or GPU acceleration. At its core is Alibaba's T-Head TH1520 processor featuring four 2.50 GHz Xuantie C910 RISC-V general-purpose CPU cores and an unnamed Imagination GPU. The chip was originally aimed at laptop designs. Memory options include 8 GB or 16 GB LPDDR4X RAM and 32 GB or 128 GB of storage. The Lichee Pocket 4A has a 7-inch 1280x800 LCD touchscreen, Wi-Fi/Bluetooth connectivity, and an array of wired ports like USB and Ethernet. It weighs under 500 grams. The device can run Android or Linux distributions like Debian, Ubuntu, and others.

As an early RISC-V gaming entrant, performance expectations should be modest—the focus is retro gaming and small indie titles, not modern AAA games. Specific gaming capabilities remain to be fully tested. However, the release helps showcase RISC-V's potential for consumer electronics and competitive positioning against proprietary ISAs like ARM. Pricing is still undefined, but another Sipeed handheld console retails for around $250 currently. Reception from enthusiasts and developers will demonstrate whether there's a viable market for RISC-V gaming devices. Success could encourage additional hardware experimentation efforts across emerging open architectures. With a 6000 mAh battery, battery life should be decent. Other specifications can be seen in the table below, and the pre-order link is here.

Renesas Electronics Corporation, a premier supplier of advanced semiconductor solutions, announced today that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V instruction set architecture (ISA). Renesas is among the first in the industry to independently develop a CPU core for the 32-bit general-purpose RISC-V market, providing an open and flexible platform for IoT, consumer electronics, healthcare and industrial systems. The new RISC-V CPU core will complement Renesas' existing IP portfolio of 32-bit microcontrollers (MCUs), including the proprietary RX Family and the RA Family based on the Arm Cortex -M architecture.

RISC-V is an open ISA which is quickly gaining popularity in the semiconductor industry, due to its flexibility, scalability, power efficiency and open ecosystem. While many MCU providers have recently created joint investment alliances to accelerate their development of RISC-V products, Renesas has already developed a new RISC-V core on its own. This versatile CPU can serve as a main application controller, a complementary secondary core in SoCs, on-chip subsystems, or even in deeply embedded ASSPs. This positions Renesas as a leader in the emerging RISC-V market, following previous introductions of its 32-bit voice-control and motor-control ASSP devices, as well as the RZ/Five 64-bit general purpose microprocessors (MPUs), which were built on CPU cores developed by Andes Technology Corp.

Rapidus Corporation, a company involved in the research, development, design, manufacture, and sales of advanced logic semiconductors, today announced an agreement with Tenstorrent Inc., a next-generation computing company building computers for AI, to jointly develop semiconductor IP (design assets) in the field of AI edge devices based on 2 nm logic semiconductors.

In addition to its AI processors and servers, Tenstorrent built and owns the world's most performant RISC-V CPU IP and licenses that technology to its customers around the world. Through this technological partnership with Rapidus, Tenstorrent will accelerate the development of cutting-edge devices to meet the needs of the ever-evolving digital society.

Synopsys, Inc. (Nasdaq: SNPS) today announced it has extended its ARC Processor IP portfolio to include new RISC-V ARC-V Processor IP, enabling customers to choose from a broad range of flexible, extensible processor options that deliver optimal power-performance efficiency for their target applications. Synopsys leveraged decades of processor IP and software development toolkit experience to develop the new ARC-V Processor IP that is built on the proven microarchitecture of Synopsys' existing ARC Processors, with the added benefit of the expanding RISC-V software ecosystem.

Synopsys ARC-V Processor IP includes high-performance, mid-range, and ultra-low power options, as well as functional safety versions, to address a broad range of application workloads. To accelerate software development, the Synopsys ARC-V Processor IP is supported by the robust and proven Synopsys MetaWare Development Toolkit that generates highly efficient code. In addition, the Synopsys.ai full-stack AI-driven EDA suite is co-optimized with ARC-V Processor IP to provide an out-of-the-box development and verification environment that helps boost productivity and quality-of-results for ARC-V-based SoCs.

Ventana Micro Systems Inc. today announced the second generation of its Veyron family of RISC-V processors. The new Veyron V2 is the highest performance RISC-V processor available today and is offered in the form of chiplets and IP. Ventana Founder and CEO Balaji Baktha will share the details of Veyron V2 today during his keynote speech at the RISC-V Summit North America 2023 in Santa Clara, California.

"Veyron V2 represents a leap forward in our quest to lead the industry in high-performance RISC-V CPUs that are ready for rapid customer adoption," said Balaji Baktha, Founder and CEO of Ventana. "It substantiates our commitment to customer innovation, workload acceleration, and overall optimization to achieve best in class performance per Watt per dollar. V2 enhancements unleash innovation across data center, automotive, 5G, AI, and client applications."

Alibaba's T-Head unit, responsible for the design and development of in-house IC design, has announced the first domestic SSD controller based on the PCIe 5.0 specification standard. Called the Zhenyue 510, the SSD controller is aimed at enterprise SSD offerings. Interestingly, the Zhenyue 510 is powered by T-Head's custom Xuantie C910 cores based on RISC-V instruction set architecture (ISA). Supporting the PCIe 5.0 standard for interfacing, the SSD controller uses DDR5 memory as a cache buffer. Regarding the performance, there are no official figures yet, but the company claims to have 30% lower input/output latencies compared to competing offerings. T-Head claims the SSD has an IO processing capability of "3400 Kilo IOs per second, a data bandwidth of 14 Gbytes/s, and an extremely high energy efficiency of 420 Kilo IO per second for every Watt".

This is an essential step towards Chinese self-sufficiency as T-Head has designed various ICs for processing different tasks. Still, now Alibaba's chip design unit has a domestic design for storage as well. Claiming low latency figures, the Zhenyue 510 is suitable for enterprise workloads like big data analysis, as well as AI inference/training systems workloads. The development of Zhenyue 510 started in 1H 2021, and it took the company more than two years to complete the design and validation of the chip to prepare it for deployment. This is the second Chinese-made SSD controller after Yingren Technology (InnoGrit) announced their chip in September.