Researchers at the University of California, Berkeley in 2010 have started an interesting project. They created a goal to develop a new RISC-like Instruction Set Architecture that is simple and efficient while being open-source and royalty-free. Born out of that research was RISC-V ISA, the fifth iteration of Reduced Instruction Set Computing (RISC) ideology. Over the years, the RISC-V ISA has become more common, and today, many companies are using it to design their processors and release new designs every day. One of those companies is Micro Magic Inc., a provider of silicon design tools, IP, and design services. The company has developed a RISC-V processor that is rather interesting.

Apart from the RISC-V ISA, the processor has an interesting feature. It runs at the whopping 5 GHz frequency, a clock speed unseen on the RISC-V chips before, at the power consumption of a mere one (yes that is 1) Watt. The chip ran at just 1.1 Volts, which means that a very low current needs to be supplied to the chip so it can achieve the 5 GHz mark. If you are wondering about performance, well the numbers show that at 5 GHz, the CPU can produce a score of 13000 CoreMarks. However, that is not the company's highest-performance RISC-V core. In yesterday's PR, Micro Magic published that their top-end design can achieve 110000 CoreMarks/Watt, so we are waiting to hear more details about it.

RISC-V architecture is a relatively new Instruction Set Architecture (ISA) developed at the University of California Berkeley. Starting as a "short, three-month project" the RISC-V ISA is a fifth generation of the Reduced Instruction Set Computing (RISC) ideology. A company working on this technology and helping to grow the ecosystem is SiFive. Today, they announced a big step forward for the ecosystem that will enable developers to make and optimize even more software for this architecture and platform. Called the HiFive Unmatched, the development board represents the first entry of RISC-V ISA to the world of personal computing, with its Mini-ITX form factor and PC-like connectors of power supply and I/O.

The board is home to SiFive's FU740 SoC, a five-core heterogeneous, coherent processor with four SiFive U74 cores, and one SiFive S7 core. This SoC is capable of smooth Linux OS operation, giving the developers a good platform to do their optimizations for. There is 8 GB of onboard DDR4 RAM (unknown frequencies and timing), a MicroSD card slot, and one PCIe 3.0 x4 M.2 slot for system storage. To connect the board to the outside world, you get one Gigabit Ethernet port. For user I/O there are four USB 3.2 Gen 1 Type-A ports (1 Charging port) and one MicroUSB Console port. To power the board, you need a proper power supply with a 24-pin power connector. If you plan to build a PC based on the Unmatched board, you would need a standard ITX case, as it comes in the standard Mini-ITX (170x170 mm) form factor. For more information, please check out SiFive's website.

SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Yunsup Lee, CTO of SiFive, and Dr. Krste Asanovic, Chief Architect of SiFive, will present at the technology industry's premier processor conference, the Linley Fall Virtual Processor Conference. The conference will be held on October 20th - 22nd and 27th - 29th, 2020 and will feature high-quality technical content from leading semiconductor companies worldwide.

"Industry demand for AI performance has skyrocketed over the last few years driven by rapid adoption from the data center to the edge. This year's Linley Fall Processor Conference will feature our biggest program yet and will introduce a host of new technology disclosures and product announcements of innovative processor architectures and IP technologies," said Linley Gwennap, principal analyst and conference chairperson. "In spite of the challenges posed by the pandemic, development of these technologies continues to accelerate and we're excited to be sharing these presentations with a global audience via our live-streamed format."

Underscoring its mission to enable the world to solve its biggest data challenges by building a data infrastructure with next-gen security, Western Digital (NASDAQ: WDC) today introduced the ArmorLock Security Platform. A data encryption platform that rethinks how data security should be done, the ArmorLock Security Platform was created to help with the diverse security demands of data-centric and content-critical storage use cases in industries as varied as finance, government, healthcare, IT enterprise, legal, and media and entertainment. As data security concerns continue to rise in visibility, Western Digital plans to apply the platform across a range of storage solutions.

The first product to leverage this advanced technology, the new G-Technology ArmorLock encrypted NVMe SSD, is designed to deliver an easy-to-use, high-performance, high-grade security storage solution for creators in the media and entertainment industry. Facing the threat of hijacked media files and leaked films, studios, agencies, and especially investors are demanding a better way to protect critical content. While much of the industry's focus has been on cloud security, data often remains vulnerable on the portable storage devices holding critical commercial content.

SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced it raised $61 million in a Series E round led by SK hynix, joined by new investor Prosperity7 Ventures, with additional funding from existing investors, Sutter Hill Ventures, Western Digital Capital, Qualcomm Ventures, Intel Capital, Osage University Partners, and Spark Capital.

"Global demand for storage and memory in the data center is increasing as AI-powered business intelligence and data processing growth continues", said Youjong Kang, VP of Growth Strategy, SK hynix. "SiFive is well-positioned to grow with opportunities created from data center, enterprise, storage and networking requirements for workload-focused processor IP."

Tachyum Inc. today announced that it has successfully completed a demonstration showing its Prodigy Universal Processor running faster than any other processor, HPC or AI chips, including ones from NVIDIA and Intel. This is the latest of many recent milestones achieved by Tachyum as the company continues its march towards Prodigy's product release next year.

Tachyum demonstrated how its computational operation and the speed of its product design, using an industry-standard Verilog simulation of the actual Prodigy post layout hardware, is the superior solution to current competitive offerings. Not only does Prodigy execute instructions at very high speeds, but Tachyum now has an infrastructure implemented for automatically checking correct results from the Verilog RTL. These automated tests check Verilog output for correctness compared to Tachyum's C-model, which was used to measure performance, and is now the 'Golden Model' for the Verilog hardware simulation to ensure it produces identical, step-by-step results.

Tachyum Inc. announced that its Prodigy Universal Processor has successfully completed software emulation testing across x86, ARM and RISC-V binary environments. This important milestone demonstrates that Prodigy will enable customers to run their legacy applications transparently at launch with better performance than any contemporary or future ARM or RISC-V processors. Coupled with hyperscale data center workhorse programs such as Hadoop, Apache and more, which Tachyum is recompiling to Prodigy native code, this capability will ensure that Prodigy customers can run a broad spectrum of applications, right out of the box. Tachyum customers consistently indicate that they would run 100% native applications within 9-18 months of transitioning to the Tachyum platform to exceed performance of the fastest Xeon processor. The emulation is to smoothly transition to native software for Tachyum Prodigy.

Today the Hot Chips program committee officially announced the August conference line-up, posted to hotchips.org. For this first-ever live-streamed Hot Chips Symposium, the program is better than ever!

In a session on deep learning training for data centers, we have a mix of talks from the internet giant Google showcasing their TPUv2 and TPUv3, and a talk from startup Cerebras on their 2nd gen wafer-scale AI solution, as well as ETH Zurich's 4096-core RISC-V based AI chip. And in deep learning inference, we have talks from several of China's biggest AI infrastructure companies: Baidu, Alibaba, and SenseTime. We also have some new startups that will showcase their interesting solutions—LightMatter talking about its optical computing solution, and TensTorrent giving a first-look at its new architecture for AI.

European Processor Initiative (EPI) is a Europe's project to kickstart a homegrown development of custom processors tailored towards different usage models that the European Union might need. The first task of EPI is to create a custom processor for high-performance computing applications like machine learning, and the chip prototypes are already on their way. The EPI chairman of the board Jean-Marc Denis recently spoke to the Next Platform and confirmed some information regarding the processor design goals and the timeframe of launch.

Supposed to be manufactured on TSMC's 6 nm EUV (TSMC N6 EUV) technology, the EPI processor will tape-out at the end of 2020 or the beginning of 2021, and it is going to be heterogeneous. That means that on its 2.5D die, many different IPs will be present. The processor will use a custom ARM CPU, based on a "Zeus" iteration of Neoverese server core, meant for general-purpose computation tasks like running the OS. When it comes to the special-purpose chips, EPI will incorporate a chip named Titan - a RISC-V based processor that uses vector and tensor processing units to compute AI tasks. The Titan will use every new standard for AI processing, including FP32, FP64, INT8, and bfloat16. The system will use HBM memory allocated to the Titan processor, have DDR5 links for the CPU, and feature PCIe 5.0 for the inner connection.

Diversity is the name of the game when it comes to the edge Artificial Intelligence (AI) chipset industry. In 2019, the AI industry is witnessing the continual migration of AI workloads, particularly AI inference, to edge devices, including on-premise servers, gateways, and end-devices and sensors. Based on the AI development in 17 vertical markets, ABI Research, a global tech market advisory firm, estimates that the edge AI chipset market will grow from US $2.6 billion in 2019 to US $7.6 billion by 2024, with no vendor commanding more than 40% of the market.

The frontrunner of this market is NVIDIA, with a 39% revenue share in the first half of 2019. The GPU vendor has a strong presence in key AI verticals that are currently leading in AI deployments, such as automotive, camera systems, robotics, and smart manufacturing. "In the face of different use cases, NVIDIA chooses to release GPU chipsets with different computational and power budgets. In combination with its large developer ecosystem and partnerships with academic and research institutions, the chipset vendor has developed a strong foothold in the edge AI industry," said Lian Jye Su, Principal Analyst at ABI Research.

NVIDIA is facing stiff competition from Intel with its comprehensive chipset portfolio, from Xeon CPU to Mobileye and Movidius Myriad. At the same time, FPGA vendors, such as Xilinx, QuickLogic, and Lattice Semiconductor, are creating compelling solutions for industrial AI applications. One missing vertical from NVIDIA's wide footprint is consumer electronics, specifically smartphones. In recent years, AI processing in smartphones has been driven by smartphone chipset manufacturers and smartphone vendors, such as Qualcomm, Huawei, and Apple. In smart home applications, MediaTek and Amlogic are making their presence known through the widespread adoption of voice control front ends and smart appliances.

It is no secret that silicon manufacturing is an expensive and difficult process which requires big investment and a lot of effort to get right. Take Intel's 10 nm for example. It was originally planned to launch in 2015, but because of technical difficulties, it got delayed for 2019. That shows how silicon scaling is getting more difficult than ever, while costs are rising exponentially. Development of newer nodes is expected to cost billions of Dollars more, just for the research alone and that is not even including the costs for the setting up a manufacturing facility. In order to prepare for the moment when the development of ever-decreasing size nodes becomes financially and physically unfeasible, researchers are exploring new technologies that could replace and possibly possess even better electrical properties than silicon. One such material (actually a structure made from it) is Carbon Nanotube or CNT in short.

Researchers from MIT, in collaboration with scientists from Analog Devices, have successfully built a CPU based on RISC-V architecture entirely using CNTs. Called RV16X Nano, this CPU is currently only capable of executing a classic "Hello World" program. CNT is a natural semiconductor, however, when manufactured, it is being made as a metallic nanotube. That is due to the fact that metallic nanotubes are easier to integrate into the manufacturing ecosystem. Its has numerous challenges in production because CNTs tend to position themselves randomly in XYZ axes. Researchers from MIT and Analog Devices solved this problem by making large enough surfaces so that enough random tubes are positioned well.

Western Digital Corp. today announced that Martin Fink, executive vice president and chief technology officer, will be transitioning to retirement and moving to an advisory role with the Company. Mr. Fink will continue to report to Steve Milligan, chief executive officer, and advise Mr. Milligan and the executive team on matters relating to data center architectures, including RISC-V. Dr. Siva Sivaram, executive vice president, Silicon Technology and Manufacturing, has been appointed to the newly created role of President, Technology and Strategy, effective immediately. In this expanded strategic role, Dr. Sivaram will oversee Western Digital's key technology initiatives and corporate strategy.

Dr. Sivaram has more than 35 years of experience in semiconductor technology and manufacturing. Prior to joining Western Digital in 2016 following the acquisition of SanDisk, he held executive positions at Intel and Matrix Semiconductor. Additionally, he was the founder and CEO of Twin Creeks Technologies, a solar panel and equipment company.

"Siva has been instrumental in leading the ongoing development of our 3D flash memory and other next generation technologies," said Steve Milligan, Western Digital chief executive officer. "Looking to the future, I am confident that with Siva's expertise, we will be well positioned to further strengthen Western Digital's leading technology position and innovative product portfolio."

The European Processor Initiative(EPI), crucial element of the European exascale strategy, delivers its first architectural design to the European Commission and welcomes new partners Almost six months in, the project that kicked off last December has already delivered its first architectural designs to the European Commission, thus marking initial milestones successfully executed. The project that will be the cornerstone of the EU's strategic plans in HPC initially brought together 23 partners from 10 European countries, but has now welcomed three more strong additions to its EPI family. EPI consortium aims to bring a low-power microprocessor to the market and ensure that the key competences for high-end chip design remain in Europe. The European Union's Horizon 2020 program funds this project with a special Framework Partnership Agreement. The initial stage is a three-year Specific Grant Agreement, which lasts until November 2021.

As the trade war between the US and China continues to unfold, we are seeing major US companies ban or stop providing service to China's technology giant Huawei. Now, it looks like the trade war has crossed the ocean and reached the UK. This time, UK based ARM Holdings, the provider of mobile chip IP for nearly all smartphones and tablets, has revoked the license it has given Huawei.

According to the BBC, ARM Holdings employees were instructed to suspend all interactions with Huawei, and to send a note informing Huawei that "due to an unfortunate situation, they were not allowed to provide support, deliver technology (whether software, code, or other updates), engage in technical discussions, or otherwise discuss technical matters with Huawei, HiSilicon or any of the other named entities." The news came from an internal ARM document the BBC has obtained.

Western Digital Corp. today announced at the RISC-V Summit three new open-source innovations designed to support Western Digital's internal RISC-V development efforts and those of the growing RISC-V ecosystem. In his keynote address, Western Digital's Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator.

These innovations are expected to accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments. Western Digital has taken an active role in helping to advance the RISC-V ecosystem, including multiple related strategic investments and partnerships, and demonstrated progress toward its stated goal of transitioning one billion of the company's processor cores to the RISC-V architecture.

You may never have heard of SiFive before -and that's perfectly understandable. The startup has just been brought from the ground-up following a round of funding, which netted it some $50.6 million dollars in the old, pre-ICO-preferred ways for funding: venture capital. The objective: to offer other startup companies a way to bring their idealized silicon into actual, custom silicon based on the RISC-V architecture, and then work with them towards achieving actual large-scale production.

The company will have available for customers options of IP and pre-baked designs which they can mix and match according to their needs, alongside small-scale production capability for companies to have their actual product - and test it in real-world conditions - before entering large-scale production. This move by SiFive aims to enable a larger variety of task-specific processor designs, ushering in a new, more liberal area of chip design and production.

Recent articles in the media have raised awareness around the processor security vulnerabilities named Meltdown and Spectre. These vulnerabilities are particularly troubling as they are not due to a bug in a particular processor implementation, but are a consequence of the widespread technique of speculative execution. Many generations of processors with different ISAs and from several different manufacturers are susceptible to the attacks, which exploit the fact that instructions speculatively executed on incorrectly predicted code paths can leave observable changes in micro-architectural state even though the instructions' architectural state changes will be undone once the branch prediction is found incorrect. No announced RISC-V silicon is susceptible, and the popular open-source RISC-V Rocket processor is unaffected as it does not perform memory accesses speculatively.

Western Digital Corp. announced today at the 7th RISC-V Workshop that the company intends to lead the industry transition toward open, purpose-built compute architectures to meet the increasingly diverse application needs of a data-centric world. In his keynote address, Western Digital's Chief Technology Officer Martin Fink expressed the company's commitment to help lead the advancement of data-centric compute environments through the work of the RISC-V Foundation. RISC-V is an open and scalable compute architecture that will enable the diversity of Big Data and Fast Data applications and workloads proliferating in core cloud data centers and in remote and mobile systems at the edge. Western Digital's leadership role in the RISC-V initiative is significant in that it aims to accelerate the advancement of the technology and the surrounding ecosystem by transitioning its own consumption of processors - over one billion cores per year - to RISC-V.