Monday, December 4th 2017

Western Digital Delivers New SweRV Core RISC-V Processor

Western Digital Corp. today announced at the RISC-V Summit three new open-source innovations designed to support Western Digital's internal RISC-V development efforts and those of the growing RISC-V ecosystem. In his keynote address, Western Digital's Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator.

These innovations are expected to accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments. Western Digital has taken an active role in helping to advance the RISC-V ecosystem, including multiple related strategic investments and partnerships, and demonstrated progress toward its stated goal of transitioning one billion of the company's processor cores to the RISC-V architecture.
"As Big Data and Fast Data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today's wide-ranging data-centric applications," said Fink. "Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realized by bringing data closer to processing power. These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries."

RISC-V is an open, scalable instruction set architecture that enables the diversity of Big Data and Fast Data applications and workloads proliferating in core data centers and in remote and mobile systems at the edge. It provides an alternative to current, standard, general purpose compute architectures. With RISC-V, open standard interfaces can be utilized to enable specialty processing, memory centric solutions, unique storage and flexible interconnect applications.

Western Digital is planning to open source its new RISC-V SweRV Core, which has a 2-way superscalar design. Western Digital's RISC-V SweRV Core is a 32-bit, 9 stage pipeline core that allows several instructions to be loaded at once and execute simultaneously, shortening the time taken to run programs. It is a compact, in-order core and runs at 4.9 CoreMarks/Mhz1. Its power-efficient design offers clock speeds of up to 1.8Ghz1 on a 28mm CMOS process technology. The company plans to use the SweRV Core in various internal embedded designs, including flash controllers and SSDs. Open sourcing the core is expected to drive development of new data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more.

Western Digital's OmniXtend is a new open approach to providing cache coherent memory over an Ethernet fabric. This memory-centric system architecture provides open standard interfaces for access and data sharing across processors, machine learning accelerators, GPUs, FPGAs and other components. It is an open solution for efficiently attaching persistent memory to processors and offers potential support of future advanced fabrics that connect compute, storage, memory and I/O components.

Western Digital also introduced today its open-sourced SweRV Instruction Set Simulator (ISS) , which offers full test bench support for use with RISC-V cores. An ISS is a computer program that simulates the execution of instructions of a processor. It allows external events to be modeled, such as interrupts and bus errors, and assures the RISC-V core is functioning properly. The company utilized the SweRV ISS to rigorously simulate and validate the SweRV Core, with more than 10 billion instructions executed. Western Digital expects both the SweRV Core and SweRV ISS will help to accelerate the industry's move to an open source instruction set architecture.

"Speeds, feeds, and brute compute is no longer the winning formula for edge and endpoint computing. As more data moves to the edge for real-time processing and inferencing, configurable architectures will be better suited to meet the needs of heavy and often dynamic application workloads, especially for those driven by artificial intelligence and Internet of Things," said Mario Morales, program vice president, enabling technologies and semiconductors, IDC. "Power efficiency, configurability, and low power will become the key metrics for edge and endpoint computing architectures."

Availability and Resources
Western Digital's SweRV ISS and OmniXtend architecture are available now for download at the following locations:
  • OmniXtend: https://github.com/westerndigitalcorporation/omnixtend
  • SweRV ISS: https://github.com/westerndigitalcorporation/swerv-ISS
Western Digital's SweRV core will be available in CY Q1 2019. For further information visit this page.
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5 Comments on Western Digital Delivers New SweRV Core RISC-V Processor

#1
TheLostSwede
Interesting, but an open source CPU design is hardly going to be picked up by many, considering that it'll most likely not include parts like the memory controller and some other tricky bits that tends to be IP from specialist hardware IP licensing companies. It's possible that it'll make it easier for other companies in RISC-V to design their own chips though, so I guess it's not all bad. Also, due to the licensing of the RISC-V architecture, WD had to open source their parts, so it's not as if they're being overly generous here. I highly doubt WD will offer their end SoCs to other companies as well, since that's not their business.
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#2
R0H1T
TheLostSwede said:
Interesting, but an open source CPU design is hardly going to be picked up by many, considering that it'll most likely not include parts like the memory controller and some other tricky bits that tends to be IP from specialist hardware IP licensing companies. It's possible that it'll make it easier for other companies in RISC-V to design their own chips though, so I guess it's not all bad. Also, due to the licensing of the RISC-V architecture, WD had to open source their parts, so it's not as if they're being overly generous here. I highly doubt WD will offer their end SoCs to other companies as well, since that's not their business.
You mean how it's virtually the most popular CPU design around, especially wrt "nationalizing" CPUs or in academia :rolleyes:
Adopters

Commercial
  • SiFive, a company established specifically for developing RISC-V hardware, has processor models released in 2017.[33][34] These include a quad-core RISC-V SoCa quad-core, 64-bit SoC.
  • Andes Technology Corporation, a founding member of the RISC-V Foundation[36] which joined the consortium in 2016, released its first two RISC-V cores in 2017. The cores, the N25 and NX25, come with a complete design ecosystems and a number of RISC-V partners. Andes is actively driving the development of RISC-V ecosystem and expects to release several new RISC-V products in 2018.
  • Codasip and UltraSoC have developed fully supported intellectual property for RISC-V embedded SOCs that combine Codasip's RISC-V cores and other IP with UltraSoC's debug, optimization and analytics.
  • Imperas has developed a family of fast processor models for the different subsets of RV32GC and RV64GC ISA variants that are part of the OVPsim instruction accurate simulator distributions used for embedded software development.
  • GreenWaves Technologies announced the availability of GAP8, a 32-bit 1 controller plus 8 compute cores, 32-bit SoC and developer board in February 2018. Their GAPuino GAP8 development board started shipping in May 2018.
  • Hex Five announced general availability MultiZone Security - the first RISC-V Trusted Execution Environment utilizing the standard RISC-V ISA and privileged mode extensions.
  • CloudBEAR is a processor IP company that develops its own RISC-V cores for a range of applications.
In development
https://riscv.org/members-at-a-glance/
https://en.wikipedia.org/wiki/RISC-V
Posted on Reply
#3
TheLostSwede
R0H1T said:
You mean how it's virtually the most popular CPU design around, especially wrt "nationalizing" CPUs or in academia :rolleyes:

https://riscv.org/members-at-a-glance/
https://en.wikipedia.org/wiki/RISC-V
I think you misunderstood, not talking abut RISC-V, I'm talking about the fact that WD said they will open source their work, which I doubt has any impact in the grander scale of things. RISC-V has a lot of potential, but we'll see how open the final products will be, since things like memory controllers, PCIe root complexes and GPUs are closely guarded secrets, but are needed to make functional chips.
Posted on Reply
#4
R-T-B
TheLostSwede said:
since things like memory controllers, PCIe root complexes and GPUs
These things can all be added externally. It was done that way as recently as Core2, in fact.
Posted on Reply
#5
TheLostSwede
R-T-B said:
These things can all be added externally. It was done that way as recently as Core2, in fact.
Yes, but what's the point of an open source CPU core, where a company has to license all the bits that makes it work, most likely for 100's of thousands of dollars?
Again, the parts WD is sharing under open source, aren't likely to be any of those bits, just a few bits and pieces they added to RISC-V, as they have to do so according to the licensing.
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