News Posts matching #SpacemiT

Return to Keyword Browsing

DeepComputing Launches DC-ROMA RISC-V Mainboard III for Framework Laptop 13

DeepComputing today announced the official launch of the DC-ROMA RISC-V Mainboard III for the Framework Laptop 13, marking a major milestone in bringing practical, high-performance RISC-V computing into a modular laptop form factor. Starting at $699, the new mainboard represents a significant step toward making RISC-V a developer-ready, everyday computing platform—combining open architecture, modern performance, and seamless integration with the Framework ecosystem.

Built on the RISC-V architecture and designed for full compatibility with the Framework Laptop 13, the DC-ROMA RISC-V Mainboard III is powered by the SpacemiT K3 RISC-V AI SoC—the world's first RISC-V SoC to support the RVA23 profile. This standardization milestone helps provide a more consistent software target for developers, accelerating ecosystem maturity.

RISC-V Breakthrough: SpacemiT Develops Server CPU Chip V100 for Next-Gen AI Applications

Recently, SpacemiT, a RISC-V AI CPU company from China, announced breakthrough progress in the development of its server CPU chip SpacemiT Vital Stone V100. It now provides a complete RISC-V CPU chip hardware and software platform that fully supports server specifications.

RISC-V CPU core X100, AIA and APLIC supporting interrupt virtualization, IOMMU supporting memory virtualization, IOPMP supporting security functions, LPC and eSPI supporting communication with mainstream BMCs, etc.
  • The 64-bit server-grade RISC-V CPU core X100 delivers a single-core performance of >9 points/GHz on SPECINT2006 at 2.5 GHz 12 nm. X100 supports the RVA23 Profile, full virtualization (Hypervisor 1.0, AIA 1.0, IOMMU), RAS features, Vector 1.0 extension, vector encryption and decryption, security, 64-core interconnect, and more.
  • The IOMMU IP adheres to the RISC-V IOMMU architecture specification and the AXI4-Stream DTI interface, supporting configurable DID, PID, virtual address, physical address width, and various levels of translation cache sizes. It can be flexibly integrated into different locations within the SoC bus system to enable distributed peripheral virtualization and accelerator acceleration.
Return to Keyword Browsing
Nov 11th, 2026 18:50 CST change timezone

New Forum Posts

Popular Reviews

TPU on YouTube

Controversial News Posts