Cadence (Nasdaq: CDNS) today announced the industry's first LPDDR5X 9600 Mbps memory IP system solution designed specifically for enterprise and data center applications with high reliability. This innovative solution integrates Cadence's production-proven LPDDR5X IP and Microsoft's advanced redundant array of independent double data rate (RAIDDR) error correction code (ECC) coding schema, delivering a powerful combination of high performance, low power consumption and robust reliability. Microsoft is the first customer to deploy the new system solution.

In the AI infrastructure build-out, LPDDR5X is gaining traction in the data center due to its ability to boost energy efficiency and performance for AI, HPC and other memory-intensive workloads. While LPDDR5X-based systems reduce power consumption and run times, hyperscalers have until now faced a tradeoff between power, performance and area (PPA) and the reliability, availability and serviceability (RAS) offered by DDR5 memory.

Socionext Inc., a global leader in System-on-Chip (SoC) design and advanced semiconductor solutions, introduces "Flexlets", a new class of configurable chiplets designed to advance heterogenous integration. As traditional monolithic SoC designs face physical and economic limits—reticle size constraints, yield challenges, and thermal bottlenecks- the industry is turning toward chiplet-based design, where designers can integrate their core features and interface functionalities, provided as chiplets, into a packaged device to improve performance, cost, and accelerate time-to-market.

While chiplet technology opens exciting possibilities for modular designs and scalability, many current solutions are derived from fixed-function ASSPs, limiting flexibility and customization. Socionext's Flexlets overcome this by offering a configurable library of chiplet designs at the RTL level. Unlike traditional approaches, Flexlets empower customers to tailor performance to their unique application needs - whether in high-performance computing, advanced networking, or next-generation automotive systems.

Today at the Open Compute Project (OCP) Global Summit in San Jose, AMD (NASDAQ: AMD) showcased a static display of its "Helios," rack scale platform for the first time in public. Developed based on the new Open Rack Wide (ORW) specification, introduced by Meta, "Helios" extends the AMD open hardware philosophy from silicon to system to rack, representing a major step forward in open, interoperable AI infrastructure.

Extending AMD leadership in AI and high-performance computing, "Helios" provides the foundation to deliver the open, scalable infrastructure that will power the world's growing AI demands. Designed to meet the demands of gigawatt-scale data centers, the new ORW specification defines an open, double-wide rack optimized for the power, cooling, and serviceability needs of next-generation AI systems. By adopting ORW and OCP standards, "Helios" provides the industry with a unified, standards-based foundation to develop and deploy efficient, high-performance AI infrastructure at scale.

While AMD hasn't launched its upcoming Instinct MI400 series of accelerators yet, the company has started preparing its supply chain for what comes after. Thanks to SemiAnalysis, we have a clearer picture of what AMD's Instinct MI500 UAL256 rack will look like. At the base of each compute node, there will be a single "Verano" CPU paired with four Instinct MI500 accelerators. With up to 64 nodes, split across two 32-node racks, AMD plans to enable 256 logical GPUs and 64 CPUs per mega pod, working in tandem for advanced AI and HPC workloads. Instinct MI500s UAL256 will be AMD's second-generation rack-scale system, following the upcoming Instinct MI450X IF128 aka "Helios", scheduled for the second half of 2026. The Instinct MI500 UAL256 scale-up mega pod is scheduled to arrive in 2027, just in time for Verano and Instinct MI500 accelerator.

The Instinct MI500 UAL256 scale-up mega pod splits the compute into two 32-rack cabinets, with a single central rack connecting them and hosting 18 switching trays for networking. Each of these networking trays contains four 102.4T "Vulcano" switch ASICs, designed for 800G external throughput, and manufactured on TSMC's 3 nm node. For the central processor, AMD showed few details at its Advancing AI event, which claimed that Verano introduces the "Zen 7" microarchitecture for even higher IPC and support for even newer instruction sets. For now, it's not clear if AMD will increase CPU core counts beyond the up to 256 cores per package of "Venice." Still, we're hearing that Verano will retain the Socket SP7 infrastructure, which means it will likely retain the memory and PCIe interfaces introduced in 2026, such as PCIe Gen 6, UALink, and Ultra Ethernet.

Broadcom Inc., a global leader in semiconductor and infrastructure software solutions, today announced it is now shipping the Jericho4 ethernet fabric router—a purpose-built platform for the next generation of distributed AI infrastructure. Designed to interconnect over one million XPUs across multiple data centers, Jericho4 breaks through traditional scaling limits with unmatched bandwidth, security, and lossless performance. With the Tomahawk 6, Tomahawk Ultra and Jericho4, Broadcom offers a complete networking portfolio for HPC and AI.

As AI models grow in size and complexity, the infrastructure requirements exceed the power and physical limits of a single data center. Distributing XPUs across multiple facilities—each provisioned with tens to hundreds of megawatts of power—requires a new class of router, optimized for very high-bandwidth, secure and lossless transport across regional distances.

Broadcom Inc. (NASDAQ:AVGO), a global leader in semiconductor and infrastructure software solutions, today announced the shipment of its breakthrough Ethernet switch—the Tomahawk Ultra. Engineered to transform the Ethernet switch for high-performance computing (HPC) and AI workloads, Tomahawk Ultra delivers industry-leading ultra-low latency, massive throughput, and lossless networking.

"Tomahawk Ultra is a testament to innovation, involving a multi-year effort by hundreds of engineers who reimagined every aspect of the Ethernet switch," said Ram Velaga, senior vice president and general manager of Broadcom's Core Switching Group. "This highlights Broadcom's commitment to invest in advancing Ethernet for high-performance networking and AI scale-up."

The Ultra Ethernet Consortium (UEC) today announces the release of UEC Specification 1.0, a comprehensive, Ethernet-based communication stack engineered to meet the demanding needs of modern Artificial Intelligence (AI) and High-Performance Computing (HPC) workloads. This release marks a critical step forward in redefining Ethernet for next-generation, data-intensive infrastructure.

UEC Specification 1.0 delivers a high-performance, scalable, and interoperable solution across all layers of the networking stack—including NICs, switches, optics, and cables—enabling seamless multivendor integration and accelerating innovation throughout the ecosystem.

Broadcom Inc. announced today that it is now shipping the Tomahawk 6 switch series, delivering the world's first 102.4 Terabits/sec of switching capacity in a single chip - double the bandwidth of any Ethernet switch currently available on the market. With unprecedented scale, energy efficiency, and AI-optimized features, Tomahawk 6 is built to power the next generation of scale-up and scale-out AI networks, delivering unmatched flexibility with support for 100G/200G SerDes and co-packaged optics (CPO). It offers the industry's most comprehensive set of AI routing features and interconnect options, designed to meet the demands of AI clusters with more than one million XPUs.

"Tomahawk 6 is not just an upgrade - it's a breakthrough," said Ram Velaga, senior vice president and general manager, Core Switching Group, Broadcom. "It marks a turning point in AI infrastructure design, combining the highest bandwidth, power efficiency, and adaptive routing features for scale-up and scale-out networks into one platform. Demand from customers and partners has been unprecedented. Tomahawk 6 is poised to make a rapid and dramatic impact on the deployment of large AI clusters."

AMD is gearing up to expand its Instinct MI family in the latter half of 2026 with two purpose-built UDNA-based accelerators. These new models, MI430X UL4 and MI450X, will cater respectively to high-precision HPC tasks and large-scale AI workloads. The MI430X UL4 is designed for applications that rely heavily on double-precision FP64 floating-point performance, such as scientific simulations, climate modeling, and others. It features a large array of FP64 tensor cores, ensuring consistent throughput for tightly coupled compute jobs. Because a dedicated UALink switch from partners like Astera Labs or Broadcom won't be available at launch, AMD has chosen a four-GPU point-to-point mesh configuration for the MI430X UL4. This limited scale-up approach keeps latency low and synchronization tight, making it ideal for small cluster deployments. On the AI side, the MI450X embraces Ethernet-based Ultra Ethernet for scale-out.

With UEC-ready switches already on the market, this open-standard networking solution lets users build expansive AI farms across dozens or even hundreds of nodes. By relying on established Ethernet technology instead of the new UALink ecosystem, AMD provides customers with immediate, hardware-accelerated networking for both inference and training. While UALink promises an open, vendor-neutral accelerator-to-accelerator fabric, its progress has been slow. Committee reviews and limited investment in switch silicon have delayed switch availability. Broadcom, viewed as the primary UALink switch supplier, has been cautious about its commitment, given expected lower volumes compared to Ethernet alternatives. AMD's acceleration segmentation addresses these realities. The MI430X UL4 delivers high-precision compute in compact GPU meshes. The MI450X offers large-scale AI connectivity via Ethernet. Should UALink switch development catch up in the future, AMD could revisit native GPU-to-GPU fabrics.