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Penetration Rate of Ice Lake CPUs in Server Market Expected to Surpass 30% by Year's End as x86 Architecture Remains Dominant, Says TrendForce

While the server industry transitions to the latest generation of processors based on the x86 platform, the Intel Ice Lake and AMD Milan CPUs entered mass production earlier this year and were shipped to certain customers, such as North American CSPs and telecommunication companies, at a low volume in 1Q21, according to TrendForce's latest investigations. These processors are expected to begin seeing widespread adoption in the server market in 3Q21. TrendForce believes that Ice Lake represents a step-up in computing performance from the previous generation due to its higher scalability and support for more memory channels. On the other hand, the new normal that emerged in the post-pandemic era is expected to drive clients in the server sector to partially migrate to the Ice Lake platform, whose share in the server market is expected to surpass 30% in 4Q21.

NVIDIA Brings RTX and DLSS to Arm Platform

NVIDIA at GDC dropped a major hint at where it wants to take PC gaming post the Arm acquisition. The company is demonstrating its RTX real-time raytracing technology, and the DLSS performance enhancement, on an Arm processor by MediaTek. To the PC, this means NVIDIA is laying the foundations of gaming in the post-x86 world where it holds Arm IP; foundations that were dug up by Apple and its mighty M1 chip, based on Arm CPU technology.

Making this unequivocal, was MediaTek. "RTX is the most groundbreaking technology to come to PC gaming in the last two decades," said PC Tseng, general manager of MediaTek's Intelligent Multimedia Business Unit."MediaTek and NVIDIA are laying the foundation for a new category of Arm-based high-performance PCs." The Taiwan-based Arm SoC major has developed a new Arm-based PC processor called Kompanio 1200, which it hopes will power PC platforms much like the Apple M1 or the Qualcomm Compute Platforms.

Intel "Alder Lake" Mobile Processor SKU Stack Leaked

Armed with up to 8 "Golden Cove" high-performance CPU cores and up to 8 "Gracemont" low-power cores in a hybrid x86 processor setup, the "Alder Lake" silicon enables Intel to carve out some interesting SKUs in the mobile space, by creating numerous combinations of the big and small CPU core counts, and more importantly, by adjusting the ratio of big cores to small ones. The two core types operate at significantly different performance/Watt bands, which allows Intel to target the various TDP-defined mobile processor SKU categories with just the right big:small core ratios, as revealed by a leaked "Alder Lake" mobile SKU roadmap, leaked to the web by HXL.

Intel is looking to spread the silicon across six mobile segments defined by TDP—the 5 W tablet/handheld; the 9 W ultra-thin, the 15 W mainstream tablet/laptop, the 28 W performance tablet/laptop, the 35-45 W thin enthusiast laptop, and the 45-55 W "muscle" laptop. With Intel recently announcing the discontinuation of its 1+4 (big+small) core "Lakefield" hybrid processor, its mantle in the 5 W segment will be picked up by "Alder Lake-M5," with 1 "Golden Cove" and 4 "Gracemont" cores. There will be two product tiers segmented by iGPU execution units (EUs), one with 48 EU, and the other with 64.

New Intel XPU Innovations Target HPC and AI

At the 2021 International Supercomputing Conference (ISC) Intel is showcasing how the company is extending its lead in high performance computing (HPC) with a range of technology disclosures, partnerships and customer adoptions. Intel processors are the most widely deployed compute architecture in the world's supercomputers, enabling global medical discoveries and scientific breakthroughs. Intel is announcing advances in its Xeon processor for HPC and AI as well as innovations in memory, software, exascale-class storage, and networking technologies for a range of HPC use cases.

"To maximize HPC performance we must leverage all the computer resources and technology advancements available to us," said Trish Damkroger, vice president and general manager of High Performance Computing at Intel. "Intel is the driving force behind the industry's move toward exascale computing, and the advancements we're delivering with our CPUs, XPUs, oneAPI Toolkits, exascale-class DAOS storage, and high-speed networking are pushing us closer toward that realization."

Google Selects 3rd Gen AMD EPYC Processors to Launch First Tau VM Instance

AMD and Google Cloud today announced T2D, the first instance in the new family of Tau Virtual Machines (VMs) powered by 3rd Gen AMD EPYC processors. According to Google Cloud, the T2D instance offers 56% higher absolute performance and more than 40% higher price performance for scale-out workloads. The Tau VM family provides customers with a leading combination of performance, price, and easy integration. The T2D instances, using the leadership performance of 3rd Gen AMD EPYC processors, excels at workloads including web servers, containerized micro-services, data logging-processing, large scale Java applications and more.

"At Google Cloud, our customers' compute needs are evolving," said Thomas Kurian, CEO of Google Cloud. "By collaborating with AMD, Google Cloud customers can now leverage amazing performance for scale-out applications, with great price-performance, all without compromising x86 compatibility." "We designed 3rd Gen AMD EPYC processors to meet the growing demand from cloud and enterprise customers for high-performance, cost-effective solutions with optimal TCO," said AMD President and CEO Dr. Lisa Su. "We work closely with Google Cloud and are proud they selected AMD to exclusively power the new Tau VM T2D instance which provides customers with powerful new options to run their most demanding scale-out workloads."

AMD Files Patent for its Own x86 Hybrid big.LITTLE Processor

AMD is innovating its own x86 hybrid processor technology formulated along the Arm big.LITTLE hybrid CPU core topology that inspired Hybrid processors by Intel. Under this, the processor has two kinds of CPU cores with very different performance/Watt bands—one kind focuses on performance and remains dormant under mild processing loads; while the other hand handles most lightweight processing loads that don't require powerful cores. This is easier said than done, as the two kinds of cores feature significantly different CPU core microarchitectures, and instruction sets.

AMD has filed a patent describing a method for processing workloads to be switched between the two CPU core types, on the fly. Unlike homogenous CPU core designs where workload from one core is seamlessly picked up by another over a victim cache like the L3, there is some logic involved in handover between the two core types. According to the patent application, in an AMD hybrid processor, the two CPU core types are interfaced over the processor's main switching fabric, and not a victim cache, much in the same way as the CPU cores and integrated GPU are separated in current-gen AMD APUs.

Tachyum Receives Prodigy FPGA DDR-IO Motherboard to Create Full System Emulation

Tachyum Inc. today announced that it has taken delivery of an IO motherboard for its Prodigy Universal Processor hardware emulator from manufacturing. This provides the company with a complete system prototype integrating CPU, memory, PCI Express, networking and BMC management subsystems when connected to the previously announced field-programmable gate array (FPGA) emulation system board.

The Tachyum Prodigy FPGA DDR-IO Board connects to the Prodigy FPGA CPU Board to provide memory and IO connectivity for the FPGA-based CPU tiles. The fully functional Prodigy emulation system is now ready for further build out, including Linux boot and incorporation of additional test chips. It is available to customers to perform early testing and software development prior to a full four-socket reference design motherboard, which is expected to be available Q4 2021.

UK Competition Regulator Probes AMD's Buyout of Xilinx

British competition regulator Competition and Markets Authority (CMA) on Monday, launched an enquiry into the ramifications of AMD's buy-out of FPGA maker Xilinx. The agency is soliciting opinions from the public on whether the $35 billion all-stock purchase will make goods and services less competitive for the UK. Unlike NVIDIA's Arm buyout the Xilinx acquisition is seeing no opposition from tech-giants. The Register notes that AMD could combine Xilinx's FPGAs with its x86 CPU and RDNA SIMD to create highly customizable HPC accelerators. AMD president Dr Lisa Su said "By combining our world-class engineering team and deep domain expertise, we will create an industry leader with the vision, talent and scale to define the future of high performance computing."

Intel Core-1800 Alder Lake Engineering Sample Spotted with 16C/24T Configuration

Intel's upcoming Alder Lake generation of processors is going to be the first iteration of heterogeneous x86 architecture. That means that Intel will for the first time combine smaller, low-power cores, with some big high-performance cores to provide the boost to all the workloads. If a task doesn't need much power, as some background task, for example, the smaller cores are used. And if you need to render something or you want to fire up a game, big cores are used to provide the power needed for the tasks. Intel has decided to provide such an architecture on the advanced 10 nm SuperFin, which represents a major upgrade over the existing 14 nm process.

Today, we got some information from Igor's Lab, showing the leaked specification of the Intel Core-1800 processor engineering sample. While this may not represent the final name, we see that the leaked information shows that the processor is B0 stepping. That means that the CPU will see more changes when the final sample arrives. The CPU has 16 cores with 24 threads. Eight of those cores are big ones with hyperthreading, while the remaining 8 are smaller Atom cores. They are running at the base clock of 1800 MHz, while the boost speeds are 4.6 GHz with two cores, 4.4 GHz with four cores, and 4.2 GHz with 6 cores. When all cores are used, the boost speed is locked at 4.0 GHz. The CPU has a PL1 TDP of 125 Watts, while the PL2 configuration boosts the TDP to 228 Watts. The CPU was reportedly running at 1.3147 Volts during the test. You can check out the complete datasheet below.

New Spectre Vulnerability Version Beats All Mitigations, Performance to Badly Degrade After the Fix

Researches from the University of Virginia and University of California San Diego have published their latest case study. The two universities have worked hard to discover a new Spectre vulnerability variant that can pass all of the existing Spectre mitigations and exploit all of the existing processors coming from Intel and AMD. The vulnerability exploits all of the existing x86 processors, and as it is new, there are not implementations of hardware mitigation. The whitepaper called "I see dead μops" takes the implementation of exploiting micro-op caches that could lead to a potential data leak in the processor, which is leading to a Spectre-type exploit.

Modern x86 processors break down complex instructions into smaller RISC-like units called micro-ops, in the frontend, where it makes the design of the backend part much simpler. The micro-ops are stored in the micro-ops cache. The paper is describing micro-op cache-based timing channel exploits in three primary settings: "a) across code regions within the same thread, but operating at different privilege levels, (b) across different co-located threads running simultaneously on different SMT contexts (logical cores) within the same physical core, and (c) two transient execution attack variants that leverage the micro-op cache to leak transiently accessed secrets, bypassing several existing hardware and software-based mitigations, including Intel's recommended LFENCE."

Intel CEO on NVIDIA CPUs: They Are Responding to Us

NVIDIA has recently announced the company's first standalone Grace CPU that will come out as a product in 2023. NVIDIA has designed Grace on Arm ISA, likely ARM v9, to represent a new way that data centers are built and deliver a whole new level of HPC and AI performance. However, the CPU competition in a data center space is considered one of the hardest markets to enter. Usually, the market is a duopoly between Intel and AMD, which supply x86 processors to server vendors. In the past few years, there have been few Arm CPUs that managed to enter the data canter space, however, NVIDIA is aiming to deliver much more performance and grab a bigger piece of the market.

As a self-proclaimed leader in AI, Intel is facing hard competition from NVIDIA in the coming years. In an interview with Fortune, Intel's new CEO Pat Gelsinger has talked about NVIDIA and how the company sees the competition between the two. Mr. Gelsinger is claiming that Intel is a leader in CPUs that feature AI acceleration built in the chip and that they are not playing defense, but rather offense against NVIDIA. You can check out the whole quote from the interview below.

ATP Launches Customizable SecurStor microSD Cards with Secure Boot and AES256 XTS

In response to the growing need for data protection, ATP Electronics, the global leader in specialized storage and memory solutions, has launched the SecurStor microSD cards - the latest in its line of secure NAND flash storage products for the Internet of Things (IoT), education, automotive, defense, aerospace and other applications requiring confidentiality and reliability.

"Removable storage media such as microSD cards provide great convenience and versatility for storing and transporting data. However, such convenience also exposes them to risks of unauthorized access," said Chris Lien, ATP Embedded Memory Business Unit Head. "In many instances, the boot image may be compromised, corrupting the operating system or rendering the system unusable. Malware may be introduced, or private information may be disclosed and used for damaging intents. Amidst such dangerous scenarios, we have made security a key priority for all ATP products."

NVIDIA Announces Grace CPU for Giant AI and High Performance Computing Workloads

NVIDIA today announced its first data center CPU, an Arm-based processor that will deliver 10x the performance of today's fastest servers on the most complex AI and high performance computing workloads.

The result of more than 10,000 engineering years of work, the NVIDIA Grace CPU is designed to address the computing requirements for the world's most advanced applications—including natural language processing, recommender systems and AI supercomputing—that analyze enormous datasets requiring both ultra-fast compute performance and massive memory. It combines energy-efficient Arm CPU cores with an innovative low-power memory subsystem to deliver high performance with great efficiency.

Intel's Upcoming Sapphire Rapids Server Processors to Feature up to 56 Cores with HBM Memory

Intel has just launched its Ice Lake-SP lineup of Xeon Scalable processors, featuring the new Sunny Cove CPU core design. Built on the 10 nm node, these processors represent Intel's first 10 nm shipping product designed for enterprise. However, there is another 10 nm product going to be released for enterprise users. Intel is already preparing the Sapphire Rapids generation of Xeon processors and today we get to see more details about it. Thanks to the anonymous tip that VideoCardz received, we have a bit more details like core count, memory configurations, and connectivity options. And Sapphire Rapids is shaping up to be a very competitive platform. Do note that the slide is a bit older, however, it contains useful information.

The lineup will top at 56 cores with 112 threads, where this processor will carry a TDP of 350 Watts, notably higher than its predecessors. Perhaps one of the most interesting notes from the slide is the department of memory. The new platform will make a debut of DDR5 standard and bring higher capacities with higher speeds. Along with the new protocol, the chiplet design of Sapphire Rapids will bring HBM2E memory to CPUs, with up to 64 GBs of it per socket/processor. The PCIe 5.0 standard will also be present with 80 lanes, accompanying four Intel UPI 2.0 links. Intel is also supposed to extend the x86_64 configuration here with AMX/TMUL extensions for better INT8 and BFloat16 processing.

Intel Core i9-11900K Breaks 7 GHz Barrier at 1.873 V

Intel Core i9-11900K processor, the flagship model from the 11th generation "Rocket Lake" CPU lineup, has been overclocked to more than 7 GHz by the "Rog-Fisher". Thanks to the report coming from VideoCardz, we have information that the top-end Rocket Lake processor is possibly a very good overclocker. Running at 7048 MHz, the CPU managed to achieve that frequency using "only" 1.873 V. There is no doubt that the system was being cooled by LN2, as such overclocks need it to remain stable, however, we don't have any data on that. The CPU was paired with the ASUS ROG Maximus XIII Apex motherboard, designed for extreme overclocking purposes.

It is important to note that the CPU didn't run any benchmarks, as it was just validated at that frequency by Valid x86. The sample was likely supplied by Intel, so it could be a cherry-picked model. For the official benchmark results of Rocket Lake processors, we have to wait until tomorrow (March 30th), when NDA lifts.

Despite AMD Momentum, Intel Claws Back Market Share in Both Desktop and Mobile

AMD's CPU offerings are generally considered to best Intel's competition, especially since the company's Zen 3, Ryzen-5000 series of CPUs launched to great critical and customer acclaim. However, silicon performance can only get you so far - one other issue impacting market penetration is availability of said processors. As AMD fights for constrained wafer supply from TSMC - in no small part due to their focusing of their entire portfolio on the company's highly-sought 7 nm process - users worldwide are generally seeing insufficient stocks of AMD silicon to satisfy their needs. And as such, it seems that at least some users are going with Intel solutions, due to their higher availability in the market.

According to a report from Mercury Research, AMD's constrained chip supply has led the company to a market share loss QoQ. AMD's desktop penetration fell from 20.1% to 19.3% in a single quarter, and its mobile market share saw a similar decrease, going from a 20.1% share down to 19.1%. Of course, not only from market share and shipments are a company's financials made of; AMD ushered in higher ASP (Average Selling Price) for its products, leading the company to a 50% increase in YoY revenue. This doesn't mean AMD is selling less CPUs, however; the x86 CPU market grew a massive 20.1% YoY, so AMD is actually shipping more product than in previous years - it just couldn't account for the entirety of that x86 market increase. Overall, and considering AMD's desktop, mobile, and server markets, the company's x86 market share decreased by 0.7% in Q4 2020 to 21.7% - still a very significant increase, YoY, from its previous 15.5% of the market pie.

"Nehalem" Lead Architect Rejoins Intel to Work on New High-Performance Architecture

The original "Nehalem" CPU microarchitecture from 2008 was pivotal to Intel, as it laid the foundation for Intel's mainline server and client x86 processors for the following 12-odd years. Glenn Hinton, the lead architect behind "Nehalem," announced that he is rejoining Intel after 3 years of retirement, to work on a new high-performance CPU project. Hinton states that his decision to rejoin Intel out of his retirement was influenced by Pat Gelsinger joining the company as its new CEO. Jim Keller, a CPU architecture lead behind several commercially-successful architectures, recently left Intel after a brief stint leading an undisclosed CPU core project. Keller later took up the mantle of CEO at hardware start-up Tenstorrent.

Pat Gelsinger leading Intel is expected to have a big impact on its return to technological leadership in its core businesses, as highlighted in Gelsinger's recent comments on the need for Intel to be better than Apple (which he referred to as "that lifestyle company") at making CPUs, in reference to Apple's new M1 chip taking the ultraportable notebook industry by storm. The other front Intel faces stiff competition from, is AMD, which has achieved IPC parity with Intel, and is beating it on energy-efficiency, taking advantage of the 7 nm silicon fabrication process.

Pat Gelsinger: "Intel Has to be Better at Making CPUs Than That Lifestyle Company"

Intel's future CEO Pat Gelsinger, who supersedes current CEO Bob Swan come February 15th, has reportedly compared Intel with Apple's efforts, in wake of that company's decision to leave the Intel ecosystem in favor of in-house designed ARM CPUs. As Apple M1-powered devices hit reviewers' tables, the opinions mostly went one-sided in favor of Apple's decision, clamoring for that particular CPU design to be only lightly short of a computing miracle, considering the amount of computing power provided at that chip's TDP, and running circles around Apple's previous Intel implementations.

According to The Oregonian, a local newspaper from (you guessed it) Oregon where Intel has a strong branch presence, Intel held an all-hands meeting of its Oregon workforce, attended by future Intel CEO Pat Gelsinger, who is quoted as having remarked that "We [Intel] have to deliver better products to the PC ecosystem than any possible thing that a lifestyle company in Cupertino makes. We have to be that good, in the future." Considering how Apple's M1 has raised the world's attention to the ARM architecture as a competitor with strong enough arguments to face the x86 ecosystem (as if ARM powering the world's current fastest supercomputer wasn't a strong enough argument), that seems like a strong yet adequate statement. We'll see how Intel fares with its Alder lake CPUs, which essentially bring ARM's design philosophy of an heterogeneous CPU with both high-performance and high-efficiency cores to the x86 table.

AMD Talks Zen 4 and RDNA 3, Promises to Offer Extremely Competitive Products

AMD is always in development mode and just when they launch a new product, the company is always gearing up for the next-generation of devices. Just a few months ago, back in November, AMD has launched its Zen 3 core, and today we get to hear about the next steps that the company is taking to stay competitive and grow its product portfolio. In the AnandTech interview with Dr. Lisa Su, and The Street interview with Rick Bergman, the EVP of AMD's Computing and Graphics Business Group, we have gathered information about AMD's plans for Zen 4 core development and RDNA 3 performance target.

Starting with Zen 4, AMD plans to migrate to the AM5 platform, bringing the new DDR5 and USB 4.0 protocols. The current aim of Zen 4 is to be extremely competitive among competing products and to bring many IPC improvements. Just like Zen 3 used many small advances in cache structures, branch prediction, and pipelines, Zen 4 is aiming to achieve a similar thing with its debut. The state of x86 architecture offers little room for improvement, however, when the advancement is done in many places it adds up quite well, as we could see with 19% IPC improvement of Zen 3 over the previous generation Zen 2 core. As the new core will use TSMC's advanced 5 nm process, there is a possibility to have even more cores found inside CCX/CCD complexes. We are expecting to see Zen 4 sometime close to the end of 2021.

Tachyum Prodigy Software Emulation Systems Now Available for Pre-Order

Tachyum Inc. today announced that it is signing early adopter customers for the software emulation system for its Prodigy Universal Processor, customers may begin the process of native software development (i.e. using Prodigy Instruction Set Architecture) and porting applications to run on Prodigy. Prodigy software emulation systems will be available at the end of January 2021.

Customers and partners can use Prodigy's software emulation for evaluation, development and debug, and with it, they can begin to transition existing applications that demand high performance and low power to run optimally on Prodigy processors. Pre-built systems include a Prodigy emulator, native Linux, toolchains, compilers, user mode applications, x86, ARM and RISC-V emulators. Software updates will be issued as needed.

Microsoft is Engineering Custom Processors for Servers and Surface PCs

Designing a custom processor can be a rewarding thing. You can control your ecosystem surrounding it and get massive rewards in terms of application-specific performance uplift, or lower total cost of ownership. It seems like cloud providers have figured out that at their scale, designing a custom processor can get all of the above with the right amount of effort put into it. If you remember, in 2018, Amazon has announced its Graviton processor based on Arm instruction set architecture. Today, the company has almost 10% of its AWS instances based on the Graviton 1 or 2 processors, which is a massive win for a custom design.

Following Amazon's example, the next company to join the custom server processor race is going to be Microsoft. The Redmond based giant is looking to build a custom lineup of processors that are meant to satisfy Microsoft's most demanding sector - server space. The company's Azure arm is an important part where it has big and increasing revenue. By building a custom processor, it could satisfy the market needs better while delivering higher value. The sources of Bloomberg say that Microsoft is planning to use Arm ISA, and start building independence from the x86 vendors like Intel and AMD. Just like we saw with AWS, the industry cloud giants are starting to get silicon-independent and with their scale, they can drive the ecosystem surrounding the new processors forward rapidly. The sources are also speculating that the company is building custom processors for Surface PCs, and with Windows-on-Arm (WoA) project, Microsoft has laid the groundwork in that field as well.

Worldwide Server Market Revenue Grew 2.2% Year Over Year in the Third Quarter of 2020, According to IDC

According to the International Data Corporation (IDC) Worldwide Quarterly Server Tracker, vendor revenue in the worldwide server market grew 2.2% year over year to $22.6 billion during the third quarter of 2020 (3Q20). Worldwide server shipments declined 0.2% year over year to nearly 3.1 million units in 3Q20. Volume server revenue was up 5.8% to $19.0 billion, while midrange server revenue declined 13.9% to $2.6 billion, and high-end servers declined by 12.6% to $937 million.

"Global demand for enterprise servers was a bit muted during the third quarter of 2020 although we did see areas of strong demand," said Paul Maguranis, senior research analyst, Infrastructure Platforms and Technologies at IDC. "From a regional perspective, server revenue within China grew 14.2% year over year. And worldwide revenues for servers running AMD CPUs were up 112.4% year over year while ARM-based servers grew revenues 430.5% year over year, albeit on a very small base of revenue."

Riding on the Success of the M1, Apple Readies 32-core Chip for High-end Macs

Apple's M1 SoC is possibly the year's biggest semiconductor success story, as the chip has helped Apple begin its transition away from Intel's x86 machine architecture, and create its own silicon that's optimized for its software and devices; much like its A-series SoCs powering iOS devices. The company now plans to scale up this silicon with a new 32-core version designed for high-performance Mac devices, such as the fastest MacBook Pro models; and possibly even iMac Pros and Mac Pros. The new silicon could debut in a new-generation Mac Pro in 2022. Bloomberg reports that the new silicon will allow this workstation to be half the size of the current-gen Mac Pro workstation in form, while letting Apple keep its generational performance growth trajectory.

In addition, Apple is reportedly developing a 16-core "big" + 4 "small" core version of the M1, which could power more middle-of-the-market Macs, such as the iMac desktop, and the bulk of the MacBook Pro lineup. The 16B+4s core chip could debut as early as Spring 2021. Elsewhere, the company is reportedly stepping up efforts to develop its own high-end professional-visualization GPU that it can use in its iMac Pro and Mac Pro workstations, replacing the AMD Radeon Pro solutions found in the current generation. This graphics architecture will be built from the ground-up for the Metal 3D graphics API, as well as a parallel compute accelerator. Perhaps the 2022 debut of the Arm-powered Mac Pro could feature this GPU.

Apple M1 Beats Intel "Willow Cove" in Cinebench R23 Single Core Test?

Maxon ported the its latest Cinebench R23 benchmark to the macOS "Big Sur" Apple M1 platform, and the performance results are groundbreaking. An Apple M1-powered MacBook Pro allegedly scored 1498 points in the single-core Cinebench R23 test, beating the 1382 points of the Core i7-1165G7 reference score as tested by Maxon. These scores were posted to Twitter by an M1 MacBook Pro owner who goes by "@mnloona48_" The M1 chip was clocked at 3.10 GHz for the test. The i7-1165G7 uses Intel's latest "Willow Cove" CPU cores. In the same test, the M1 scores 7508 points in the multi-core test. If these numbers hold up, we can begin to see why Apple chose to dump Intel's x86 machine architecture in favor of its own Arm-powered custom silicon, as the performance on offer holds up against the highest IPC mobile processors in the market.

AMD Announces CDNA Architecture. Radeon MI100 is the World's Fastest HPC Accelerator

AMD today announced the new AMD Instinct MI100 accelerator - the world's fastest HPC GPU and the first x86 server GPU to surpass the 10 teraflops (FP64) performance barrier. Supported by new accelerated compute platforms from Dell, Gigabyte, HPE, and Supermicro, the MI100, combined with AMD EPYC CPUs and the ROCm 4.0 open software platform, is designed to propel new discoveries ahead of the exascale era.

Built on the new AMD CDNA architecture, the AMD Instinct MI100 GPU enables a new class of accelerated systems for HPC and AI when paired with 2nd Gen AMD EPYC processors. The MI100 offers up to 11.5 TFLOPS of peak FP64 performance for HPC and up to 46.1 TFLOPS peak FP32 Matrix performance for AI and machine learning workloads. With new AMD Matrix Core technology, the MI100 also delivers a nearly 7x boost in FP16 theoretical peak floating point performance for AI training workloads compared to AMD's prior generation accelerators.
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