News Posts matching "SRAM"

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Xbox One Chip Slower Than PlayStation 4

After bagging chip supply deals for all three new-generation consoles -- Xbox One, PlayStation 4, and Wii U, things are looking up for AMD. While Wii U uses older-generation hardware technologies, Xbox One and PlayStation 4 use the very latest AMD has to offer -- "Jaguar" 64-bit x86 CPU micro-architecture, and Graphics CoreNext GPU architecture. Chips that run the two consoles have a lot in common, but also a few less-than-subtle differences.

PlayStation 4 chip, which came to light this February, is truly an engineer's fantasy. It combines eight "Jaguar" 64-bit x86 cores clocked at 1.60 GHz, with a fairly well spec'd Radeon GPU, which features 1,156 stream processors, 32 ROPs; and a 256-bit wide unified GDDR5 memory interface, clocked at 5.50 GHz. At these speeds, the system gets a memory bandwidth of 176 GB/s. Memory isn't handled like UMA (unified memory architecture), there's no partition between system- and graphics-memory. The two are treated as items on the same 8 GB of memory, and either can use up a majority of it.

Fujitsu and SuVolta Demo ULV Operation of SRAM Down to ~0.4V

Fujitsu Semiconductor Limited and SuVolta, Inc. today announced that they have successfully demonstrated ultra-low-voltage operation of SRAM (static random access memory) blocks down to 0.425V by integrating SuVolta's PowerShrink low-power CMOS platform into Fujitsu Semiconductor's low-power process technology. By reducing power consumption, these technologies will make possible the ultimate in "ecological" products in the near future. Technology details and results will be presented at the 2011 International Electron Devices Meeting (IEDM) being held in Washington DC, starting December 5th.

Controlling power consumption is the primary limiter of adding features to product types ranging from mobile electronics to tethered servers and networking equipment. The biggest contributor to power consumption is supply voltage. Previously, the power supply voltage of CMOS steadily reduced to approximately 1.0V at the 130nm technology node, but it has not reduced much further as technology has scaled to the 28nm node. To reduce the power supply voltage, one of the biggest obstacles is the minimum operating voltage of embedded SRAM blocks.

Toshiba Launches Highest Density Embedded NAND Flash Memory Devices

Toshiba Corp. (Toshiba) and Toshiba America Electronic Components, Inc. (TAEC), its subsidiary in the Americas, today announced the launch of a 64 gigabyte (GB) embedded NAND flash memory module, the highest capacity yet achieved in the industry. The chip is the flagship device in a line-up of six new embedded NAND flash memory modules that offer full compliance with the latest e-MMC standard, and that are designed for application in a wide range of digital consumer products, including Smartphones, mobile phones, netbooks and digital video cameras. Samples of the 64GB module are available from today, and mass production will start in the first quarter of 2010.

The new 64GB embedded device combines sixteen pieces of 32Gbit (equal to 4GB) NAND chips fabricated with Toshiba's cutting-edge 32nm process technology, and also integrates a dedicated controller. Toshiba is the first company to succeed in combining 16 pieces of 32Gbit NAND chips, and applied advanced chip thinning and layering technologies to realize individual chips that are only 30 micrometers thick. Full compliance with the JEDEC/MMCA Version 4.4(V4.4) standard for embedded MultiMediaCards supports standard interfacing and simplifies embedding in products, reducing development burdens on product manufacturers. Toshiba offers a comprehensive line-up of single-package embedded NAND Flash memories in densities ranging from 2GB to 64GB. All integrate a controller to manage basic control functions for NAND applications, and are compatible with the latest e-MMC standard and its new features, including defining multiple storage areas and enhanced security features.

GLOBALFOUNDRIES To Highlight 32nm/28nm Technology Leadership at GSA Expo

As the semiconductor industry begins its transition to the next technology node, GLOBALFOUNDRIES is on track to take its position as the foundry technology leader. On October 1 at the Global Semiconductor Alliance Emerging Opportunities Expo & Conference in Santa Clara, Calif., GLOBALFOUNDRIES (Booth 321) will provide the latest details on its technology roadmap for the 32nm/28nm generations and its innovative “Gate First” approach to building transistors based on High-K Metal Gate (HKMG) technology.

“With each new technology generation, semiconductor foundries are increasingly challenged with the economics to sustain R&D and the know-how to bring these technologies to market in high-volume,” said Len Jelinek, director and chief analyst, iSuppli. “With a heritage of rapidly ramping leading-edge technologies to high volumes at mature yields, combined with aggressive investments in capacity and technology, GLOBALFOUNDRIES is uniquely-positioned to challenge for next-generation foundry leadership.”

TSMC Achieves 28 nm SRAM Yield Breakthrough

Taiwan Semiconductor Manufacturing Company, Ltd. has become the first foundry not only to achieve 28 nm functional 64 Mb SRAM yield, but also to achieve it across all three 28 nm nodes.

“Achieving 64 Mb SRAM yield across all three 28 nm process nodes is striking. It is particularly noteworthy because this achievement demonstrates the manufacturing benefits of the gate-last approach that we developed for the two TSMC 28 nm high-k metal gate processes,” explained Dr. Jack Sun, vice president, Research and Development at TSMC.

“This accomplishment underscores TSMC’s process technology capability and value in 28 nm. It shows TSMC is not only able to extend conventional SiON technology to 28 nm, but is also able to deliver the right 28 nm HKMG technology at the same time,” explained Dr. Mark Liu, senior vice president, Advanced Technology Business at TSMC.

TSMC Reports Foundry’s First 32nm Functional SRAM

Taiwan Semiconductor Manufacturing Company today announced it has developed the first 32-nanometer (nm) technology that supports both analog and digital functionality. The company made its announcement through a paper presented at today’s IEEE International Electron Devices Meeting in Washington, DC. The paper also revealed that the company had proven the full functionality of the 2Mb SRAM test chip with the smallest bit-cell at the 32nm node.

NEC Develops World's Fastest SRAM-Compatible MRAM With Operation Speed of 250MHz

NEC Corporation today announced that it has succeeded in developing a new SRAM (Static Random Access Memory) - compatible MRAM that can operate at 250MHz, the world's fastest MRAM (Magnetoresistive Random Access Memory) operation speed. MRAM is expected to be the dominant next-generation memory technology as it realizes ultra fast operation speeds, nonvolatility - ability to retain data with the power off, and unlimited write endurance. Verification at the SRAM speed level proves that the newly-developed MRAM could be embedded in system LSIs as SRAM substitutes in the future.

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