Tuesday, August 23rd 2016

AMD Details ZEN Microarchitecture IPC Gains

AMD Tuesday hosted a ZEN microarchitecture deep-dive presentation in the backdrop of Hot Chips, outlining its road to a massive 40 percent gain in IPC (translated roughly as per-core performance gains), over the current "Excavator" microarchitecture. The company credits the gains to three major changes with ZEN: better core engine, better cache system, and lower power. With ZEN, AMD pulled back from its "Bulldozer" approach to cores, in which two cores share certain number-crunching components to form "modules," and back to a self-sufficient core design.

Beyond cores, the next-level subunit of the ZEN architecture is the CPU-Complex (CCX), in which four cores share an 8 MB L3 cache. This isn't different from current Intel architectures, the cores share nothing beyond L3 cache, making them truly independent. What makes ZEN a better core, besides its independence from other cores, and additional integer pipelines; subtle upscaling in key ancillaries such as micro-Op dispatch, instruction schedulers; retire, load, and store queues; and a larger quad-issue FPU.
AMD also improved the cache system. The hierarchy is similar to pre-Bulldozer AMD architectures, with L3 cache being shared between full-fledged cores, and each core having a dedicated L2 cache. The L1 cache is now write-back (and not write-through), the SRAM that makes up the L2 and L3 caches are faster.
The L3 cache SRAM has 5 times higher bandwidth than the L3 cache found on current AMD architectures. The L1 and L2 caches have 2 times the bandwidth. Load from cache to FPU is now faster. The core is endowed with 64 KB each of L1I cache, 32 KB L1D cache; 512 KB of dedicated L2 cache, and 8 MB of L3 cache shared between four cores in a CCX.
ZEN introduces simultaneous multi-threading (SMT) to AMD processors. Intel's SMT implementation is the popular HyperThreading Technology. AMD's SMT is similar in that each core is addressed to as two threads, with each thread competing for the resources on the core.
The third key area is lower-power, and this is attributed not just to the silicon-level gains yielded from the move to the 14 nm FinFET process. The design team focused on power-draw from the very inception of the ZEN core project. The L1 write-back cache, and the Op cache lower power-draw; the various components on ZEN processors feature aggressive clock-gating, although there's no power-gating.
AMD expanded the ISA CPU instruction-sets, with AVX, AVX2, BMI1, BMI2, AES, RDRAND, sMEP, SHA1/SHA256, ADX, CFLUSHopt, XSAVEC/XSAVES/XRSTORS, and SMAP. The company also introduced a few AMD-exclusive instruction sets, which can be taken advantage of for better performance, including CLzero, and PTE Coalescing.
Add your own comment

80 Comments on AMD Details ZEN Microarchitecture IPC Gains

#1
hardcore_gamer
Looks interesting indeed. BTW, does the agreement between AMD and Intel allow one company to start implementing new instructions introduced by the other ?
Thanks for waking up early and posting this, Tarun. :toast:
Posted on Reply
#3
Chaitanya
Read this couple of days back, really excited to see reviews of these new CPUs and hoping finally there will a choice for PC builders.
Posted on Reply
#4
Durvelle27
Holy hell

This really got me even more excited for Zen
Posted on Reply
#5
ZoneDymo
I love that 3rd slide, "better" , "faster"
Posted on Reply
#6
Prima.Vera
btarunr said:
...back to a self-sufficient core design
This is the key, right there. Specially for Games or unoptimized apps.
Posted on Reply
#7
chaosmassive
with introducing AMD-exclusive instruction will path of CPU diverge like GPU ?
Posted on Reply
#8
Arumio
hardcore_gamer said:
Looks interesting indeed. BTW, does the agreement between AMD and Intel allow one company to start implementing new instructions introduced by the other ?
Thanks for waking up early and posting this, Tarun. :toast:
You mean SMT? Actually AMD found it, but for some reason they don't implement it in their products in time
Posted on Reply
#9
ViperXTR
Instructions? AMD 3Dnow! anyone? though it's more of an MMX enhancement at that time
Posted on Reply
#10
medi01
I'm rather skeptical on power draw claims after rather disappointing results on 480, will wait for benchmarks (although not from TPU, sorry guys)
Posted on Reply
#11
overlord
hardcore_gamer said:
Looks interesting indeed. BTW, does the agreement between AMD and Intel allow one company to start implementing new instructions introduced by the other ?
Thanks for waking up early and posting this, Tarun. :toast:
Short answer yes, as part of their cross license agreement https://www.sec.gov/Archives/edgar/data/2488/000119312509236705/dex102.htm
That's why AMD64 coexist with x86 instructions.
http://www.kitguru.net/components/cpu/anton-shilov/amd-clarifies-cross-license-with-intel-change-of-control-terminates-agreement-for-both/
http://www.theinquirer.net/inquirer/opinion/2253532/amd-looks-to-hsa-foundation-to-avoid-amd64-mistakes
http://www.cnet.com/news/intel-ftc-settle-antitrust-case/
http://web.archive.org/web/20000302151607/http://www1.amd.com/newsroom/display/1,1528,435,00.html
Posted on Reply
#12
overlord
ViperXTR said:
Instructions? AMD 3Dnow! anyone? though it's more of an MMX enhancement at that time
Correct along with AMD64 :)
Posted on Reply
#13
$ReaPeR$
all this is fine but with no benchmarks, there is really no point in this pr crap.
Posted on Reply
#14
the54thvoid
$ReaPeR$ said:
all this is fine but with no benchmarks, there is really no point in this pr crap.
They have to release PR. It isn't for us, it's for the investors, hence the rise in share price. AMD need to be seen to be releasing a 'confident' statement on their new CPU.
Anandtech has a 'discussion' on their recent PR, mostly around the Blender bench and explain what may be happening. AT says they (AMD) aren't being as hyperbolic as Bulldozer release and are vague enough with the benchmark as to keep things within expectations.
But as said, this keeps investors happy. They all do it (Intel, Nvidia), so it's not an AMD peculiarity.
Posted on Reply
#15
Dj-ElectriC
Usually 40% would impress me between CPU gens. This actually worries me a bit.
40% is what i would think is a bare minimum to compete with today's intel's IPC
Posted on Reply
#16
$ReaPeR$
the54thvoid said:
They have to release PR. It isn't for us, it's for the investors, hence the rise in share price. AMD need to be seen to be releasing a 'confident' statement on their new CPU.
Anandtech has a 'discussion' on their recent PR, mostly around the Blender bench and explain what may be happening. AT says they (AMD) aren't being as hyperbolic as Bulldozer release and are vague enough with the benchmark as to keep things within expectations.
But as said, this keeps investors happy. They all do it (Intel, Nvidia), so it's not an AMD peculiarity.
well yes, obviously. i know they all do it, i was just stating the fact. AMD seems more restrained this time and that gives me hope for the capabilities of the zen arch, but, without independent benchmarks, there is no way to know for sure what it can do. also, i don't expect investors to be that dumb and trust the PR from AMD, or any company for that matter. maybe i'm wrong though and investors are that dumb, and they buy into the hype just to complain later that it didn't match their expectations.
Posted on Reply
#17
TheinsanegamerN
$ReaPeR$ said:
well yes, obviously. i know they all do it, i was just stating the fact. AMD seems more restrained this time and that gives me hope for the capabilities of the zen arch, but, without independent benchmarks, there is no way to know for sure what it can do. also, i don't expect investors to be that dumb and trust the PR from AMD, or any company for that matter. maybe i'm wrong though and investors are that dumb, and they buy into the hype just to complain later that it didn't match their expectations.
Given how gamers will be suckered by hype again and again and again despite having been burned enough to need a skin graft, I'd say its human nature to fall for this PR BS. investors are definitely not immune to that (theranos, anybody?)
Posted on Reply
#18
ArdWar
How "lower power" translate into IPC gain?
Posted on Reply
#19
TheinsanegamerN
ArdWar said:
How "lower power" translate into IPC gain?
Focusing on lower power draw instead of super high clocks? I doubt that lower power is part of the IPC gain, but rather is an additional bonus on top of the IPC gains.
Posted on Reply
#20
Vayra86
Well, at least we know the right ingredients are in the mix now.

And we have yet to see what AMD will really cook up with it.
Posted on Reply
#21
RejZoR
Dj-ElectriC said:
Usually 40% would impress me between CPU gens. This actually worries me a bit.
40% is what i would think is a bare minimum to compete with today's intel's IPC
Intel doesn't make 40% jumps between generations...
Posted on Reply
#22
Cvrk
reading this. knowing it will be out somewhere in october . i would postpone building a i5 6600k pc. whats 2 moremonths considering i will be having this computer for about 3-4 years.
Posted on Reply
#23
EarthDog
Ive seen now, in a couple threads, you keep saying "October". The latest I recall seeing is 4Q 2016. This means Oct-Dec. Sorry to split hairs, but, people will take that and run with it.

That said, if you have a link that shows October, post it up!

RejZoR said:
Intel doesn't make 40% jumps between generations...
Your point? Did you quote the wrong person? He didn't say nor allude to that fact. He is looking for better than Intel performance. ;)
Posted on Reply
#24
ArdWar
TheinsanegamerN said:
Focusing on lower power draw instead of super high clocks? I doubt that lower power is part of the IPC gain, but rather is an additional bonus on top of the IPC gains.
That would means an efficiency or performance gains, which is reasonable since the slideshows are actually never indicate anything about these improvements results in IPC gain.

Or maybe lower power allows them to use more complex cores.
Posted on Reply
#25
btarunr
Editor & Senior Moderator
EarthDog said:
Ive seen now, in a couple threads, you keep saying "October". The latest I recall seeing is 4Q 2016. This means Oct-Dec. Sorry to split hairs, but, people will take that and run with it.

That said, if you have a link that shows October, post it up!

Your point? Did you quote the wrong person? He didn't say nor allude to that fact. He is looking for better than Intel performance. ;)
AFAIK Q1-2017. Kaby Lake will be out before this.
Posted on Reply
Add your own comment