Wednesday, July 27th 2011

Intel Aims at 10 nm Processors by 2018

It's not just host nations of the Olympics that are decided almost decades in advance, but also Intel's silicon names and the fab process they're going to be built on. Intel has its plan for the greater part of this decade already charted out, well beyond the upcoming Ivy Bridge architecture. Intel follows the "tick-tock" product cycle, where every micro-architecture gets to be built on two succeeding fab processes, and every fab process getting to have two succeeding micro-architectures built on it, in succession. Westmere is an optical shrink of the Nehalem architecture, it was a "tick" for the 32 nm process, Sandy Bridge is its "tock", and a new architecture. Ivy Bridge is essentially an optical shrink of Sandy Bridge, it is the "tick" for 22 nm process.

Ivy Bridge will make its entry through the LGA1155 platform in 2012, it will make up the 2012 Core processor family. Haswell is the next-generation architecture that succeeds Sandy Bridge and IvyBridge, it will be built on the 22 nm process, and is expected to arrive in 2013. Roswell is its optical shrink to 14 nm, slated for 2014. Looking deep into the decade, there's Skylake architecture, that will span across 14 nm and 10 nm processes with Skymont. This model ensures that Intel has to upgrade its fabs every 2 or so years, an entirely new micro-architecture every 2 or so years as well, while providing optical shrinks every alternating year. Optical shrinks introduce new features, increased caches, and allow higher clock speeds. 10 nm for processors by 2018 sounds realistic looking at the advancement of NAND flash technologies that are pushing the boundaries of fab process development. NAND flash is much less complex than processor development, and hence serve as good precursors to a new process.

Source: ComputerBase.de
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64 Comments on Intel Aims at 10 nm Processors by 2018

#1
TheMailMan78
Big Member
twilyth said:
I don't know that they'll ever "use it" so to speak, but that doesn't mean it won't be an issue. We may not be able to use lightning, but it can still be a serious pain in the ass.
Possibly. But how do we avoid it now? Insulation no? So by the time we hit 10nm I am willing to bet the architecture will have changed so much it wont be an issue. 10nm is tiny I know but not small enough IMO where tunneling will be an issue. IMO....unless they over saturate the chip with electrons it will be fine I think.

But then again I am no engineer. I'm just an artist with a half degree in aerospace engineering. :laugh:
Posted on Reply
#2
hardcore_gamer
twilyth said:
How is adiabatic logic going to either prevent random tunneling events or compensate for them. I would be extremely interested in that.
My second paragraph has nothing to do with the first one.FYI tunnelling depends on the material and the electric field across it (voltage/width of the material) and no logic can prevent that. But even if we prevent all the short-channel effects and static power consumption by using new materials, dynamic power consumption is going to be a big problem when integrating 10s of billions of switching elements in a chip.Adiabatic logic is just a solution to reduce dynamic power consumption and it is still in early stages of development.
Posted on Reply
#3
TheMailMan78
Big Member
hardcore_gamer said:
My second paragraph has nothing to do with the first one.FYI tunnelling depends on the material and the electric field across it (voltage/width of the material) and no logic can prevent that. But even if we prevent all the short-channel effects and static power consumption by using new materials, dynamic power consumption is going to be a big problem when integrating 10s of billions of switching elements in a chip.Adiabatic logic is just a solution to reduce dynamic power consumption and it is still in early stages of development.
Basically we change the current material from drywall to uranium and it should be fine......in layman's terms :laugh:

I think that combined with the layout of the chip itself should be enough to keep it from becoming an issue.
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#4
hardcore_gamer
TheMailMan78 said:
Possibly. But how do we avoid it now? Insulation no? So by the time we hit 10nm I am willing to bet the architecture will have changed so much it wont be an issue. 10nm is tiny I know but not small enough IMO where tunneling will be an issue. IMO....unless they over saturate the chip with electrons it will be fine I think.

But then again I am no engineer. I'm just an artist with a half degree in aerospace engineering. :laugh:
Tunelling isn't the only problem. There are several other "short channel effects"
Posted on Reply
#5
TheMailMan78
Big Member
hardcore_gamer said:
Tunelling isn't the only problem. There are several other "short channel effects"
Lower voltage should reduce that issue also I would think. ALSO keep it more constant to keep it from drifting. Granted its still going to be a problem. I am looking forward to see what if any new material they use. We should know the direction they are heading in a year or so.
Posted on Reply
#6
hardcore_gamer
I think the CMOS scaling will hit a wall at 6-4nm. If new materials/devices fails to improve the scaling beyond that, next step is to increase the performance / transistor by means of efficient architectures and IP cores. Re-configurable computing also looks promising.
Posted on Reply
#7
TheMailMan78
Big Member
hardcore_gamer said:
I think the CMOS scaling will hit a wall at 6-4nm. If new materials/devices fails to improve the scaling beyond that, next step is to increase the performance / transistor by means of efficient architectures and IP cores. Re-configurable computing also looks promising.
Hey I already said that!.....just not as cool. :laugh:

TheMailMan78 said:
So by the time we hit 10nm I am willing to bet the architecture will have changed so much it wont be an issue.
Note to self......use more fancy words.
Posted on Reply
#8
Unregistered
TheMailMan78 said:
Possibly. But how do we avoid it now? Insulation no? So by the time we hit 10nm I am willing to bet the architecture will have changed so much it wont be an issue. 10nm is tiny I know but not small enough IMO where tunneling will be an issue. IMO....unless they over saturate the chip with electrons it will be fine I think.

But then again I am no engineer. I'm just an artist with a half degree in aerospace engineering. :laugh:
TheMailMan78 said:
Lower voltage should reduce that issue also I would think. ALSO keep it more constant to keep it from drifting. Granted its still going to be a problem. I am looking forward to see what if any new material they use. We should know the direction they are heading in a year or so.
Materials are irrelevant when dealing with certain quantum effects like tunneling. At least I think that's true since it happens as a consequence of the electrons wave/probability function and I don't think that this function is influenced by other materials in the vicinity. In fact, it is used in microscopy precisely because it's not influenced.

I'm more shaky on these points but I think you also get strange inductance and capacitance effects, but don't ask me to nail those down.

I think there are also issues of structural stability, migration of ions, etc, etc - at least using any kind of doped silicon. As hardcore pointed out, it's a long damn list.
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#9
TheMailMan78
Big Member
twilyth said:
Materials are irrelevant when dealing with certain quantum effects like tunneling. At least I think that's true since it happens as a consequence of the electrons wave/probability function and I don't think that this function is influenced by other materials in the vicinity. In fact, it is used in microscopy precisely because it's not influenced.

I'm more shaky on these points but I think you also get strange inductance and capacitance effects, but don't ask me to nail those down.

I think there are also issues of structural stability, migration of ions, etc, etc - at least using any kind of doped silicon. As hardcore pointed out, it's a long damn list.
I'm not sure how material COULDN'T play a role in tunneling as some materials are more conductive then others. If you use a better insulator (material) tunneling becomes less of an issue if at all from my understanding.
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#10
Unregistered
TheMailMan78 said:
I'm not sure how material COULDN'T play a role in tunneling as some materials are more conductive then others. If you use a better insulator (material) tunneling becomes less of an issue if at all from my understanding.
Because tunneling means that the electron actually disappears from location A (where you want it to be) and reappears at location B (where it couldn't possibly be).

wiki
Quantum tunnelling refers to the quantum mechanical phenomenon where a particle tunnels through a barrier that it classically could not surmount. This plays an essential role in several physical phenomena, such as shining stars,[1] and has important applications to modern devices such as the tunnel diode.[2] The effect was predicted in the early 20th century, and its acceptance as a general, physical phenomenon came mid-century.[3]

As a consequence of the wave-particle duality of matter, tunnelling is often explained using the Heisenberg uncertainty principle. Purely quantum mechanical concepts are central to the phenomenon, so quantum tunnelling is one of the defining features of quantum mechanics and the particle-wave duality of matter.
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#11
TheMailMan78
Big Member
twilyth said:
Because tunneling means that the electron actually disappears from location A (where you want it to be) and reappears at location B (where it couldn't possibly be).

wiki
But it doesn't "disappear". Its does one of two things in theory.

1. Fragments (which is what I believe)
2. Splits (which my professor believed)

But at no time does it disappear and reappear like magic.



On a side note I want to welcome Hardcore to the forums. Its nice to see someone new with brains. :toast:
Posted on Reply
#12
Unregistered
TheMailMan78 said:
But it doesn't "disappear". Its does one of two things in theory.

1. Fragments (which is what I believe)
2. Splits (which my professor believed)

But at no time does it disappear and reappear like magic.

https://upload.wikimedia.org/wikipedia/commons/5/50/EffetTunnel.gif

On a side not I want to welcome Hardcore to the forums. Its nice to see someone new with brains. :toast:
fundamental particles cannot split or fragment and an electron is a fundamental particle. However if by split you mean simultaneously travel mulitple, distinct paths simultaneously, then yes, that's perfectly kosher, but not relevant to tunneling.

According to the wave function of a particle, it simultaneously exists in many energy states at many different locations. In some cases, if you have the right conditions, you can increase the probability that the particle will manifest in a location consistent with it's wave function but which should be precluded by classical mechanics.

That's the best I can do for you. This isn't an area encompassed by either of my graduate degrees so I'm kinda winging it.
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#13
TheMailMan78
Big Member
twilyth said:
fundamental particles cannot split or fragment and an electron is a fundamental particle. However if by split you mean simultaneously travel mulitple, distinct paths simultaneously, then yes, that's perfectly kosher, but not relevant to tunneling.

According to the wave function of a particle, it simultaneously exists in many energy states at many different locations. In some cases, if you have the right conditions, you can increase the probability that the particle will manifest in a location consistent with it's wave function but which should be precluded by classical mechanics.

That's the best I can do for you. This isn't an area encompassed by either of my graduate degrees so I'm kinda winging it.
You can split an election into holons and spinons. Its been done (man made) which leads a lot to believe its done naturally (ie. tunneling). ;)
Posted on Reply
#14
Unregistered
TheMailMan78 said:
You can split an election into holons and spinons. Its been done (man made) which leads a lot to believe its done naturally (ie. tunneling). ;)
You knew I'd google that and get knocked upside the head with journal articles - didn't you? Don't even bother lying about it.

Bastard.
Posted on Edit | Reply
#15
TheMailMan78
Big Member
twilyth said:
You knew I'd google that and get knocked upside the head with journal articles - didn't you? Don't even bother lying about it.

Bastard.
I talk a lot of crap but I'm not a COMPLETE idiot. :laugh:

Like I said I have some training in Aerospace engineering (few years of college). I wanted to be an avionics expert like my father at one time. Then I realized I hated math and loved drugs. Became an artist and forgot what planet I'm on half the time.
Posted on Reply
#16
bear jesus
If Intel's aiming for 2018 for 10nm i wonder what they are aiming for in 2020 and later? surly Intel, IBM, globalfoundries, TSMC etc are all looking in to what to use next?

TheMailMan78 said:
I talk a lot of crap but I'm not a COMPLETE idiot. :laugh:

Like I said I have some training in Aerospace engineering (few years of college). I wanted to be an avionics expert like my father at one time. Then I realized I hated math and loved drugs. Became an artist and forgot what planet I'm on half the time.
:laugh: it all makes sense now :p
Posted on Reply
#17
Thatguy
TheMailMan78 said:
But it doesn't "disappear". Its does one of two things in theory.

1. Fragments (which is what I believe)
2. Splits (which my professor believed)

But at no time does it disappear and reappear like magic.

https://upload.wikimedia.org/wikipedia/commons/5/50/EffetTunnel.gif

On a side note I want to welcome Hardcore to the forums. Its nice to see someone new with brains. :toast:
or we just have no idea whats going on down at that level and what we assume is a solid electron is actually a collection of smaller particles that make a charge and when materials get small enough the particles can pass through other particle. Kind of how a bullet can't penetrate a kevlar vest but a arrow can.
Posted on Reply
#18
TheMailMan78
Big Member
Thatguy said:
or we just have no idea whats going on down at that level and what we assume is a solid electron is actually a collection of smaller particles that make a charge and when materials get small enough the particles can pass through other particle. Kind of how a bullet can't penetrate a kevlar vest but a arrow can.
That has to do with matter density which is somewhat a different debate. As for the electron being made up of "smaller particles" isn't really supported by current theories as the election is a building block of matter unless you feel holons and spinons are smaller (less volume). But that wouldn't explain the original mass of the electron when split. They are just less energized but the mass is consistent which why I believe in the fragmentation of the electron. Not the split.
Posted on Reply
#19
yogurt_21
Trackr said:
The image shows Sandy Bridge as being a Q4 2011 release.

It was actually a Q1 2011 release.

Does that mean that the whole graph is ahead three quarters?
actually it was a q2 2011 release

http://en.wikipedia.org/wiki/List_of_Intel_Xeon_microprocessors#.22Sandy_Bridge.22_.2832_nm.29

most were released april 3rd, 2011 the same time the 10 core westmere's were released.

remember this is a server roadmap and not a deskop roadmap.

at any rate I seriously doubt the roadmap is for fiscal year, they are more than likely referencing the higher end sany bridge cpu's when they speak of late q4 2011. After all doesn't that mirror lga2011's release?
Posted on Reply
#20
wolf
Performance Enthusiast
bring on Ivy brige! I like to keep my eyes on the close future as a consumer, otherwise I'd never upgrade drooling voer what will be in 5+ years time...

22nm from 32nm should enable considerably higher clockspeeds IMO, would be nice to see some 6 core CPU's make it to 1155 too. also it would be a hec of a blessing if 1155 Ivy brige chips work on curent P/H67 and Z68 mobo's.

TheMailMan78 said:
Like I said I have some training in Aerospace engineering (few years of college). I wanted to be an avionics expert like my father at one time. Then I realized I hated math and loved drugs. Became an artist and forgot what planet I'm on half the time.
explains a hec of a lot ;)
Posted on Reply
#21
hardcore_gamer
When explaining the tunelling, it is better to treat the electron as a wave and use schrodinger's wave equation. Splitting it into smaller particles complicates the solution.
Uncertainty principle gives a simple explanation. For a narrow barrier and high electric field across it, probability of finding the electron on the other side of the barrier takes a finite non-zero value.
Posted on Reply
#22
TheMailMan78
Big Member
hardcore_gamer said:
When explaining the tunelling, it is better to treat the electron as a wave and use schrodinger's wave equation. Splitting it into smaller particles complicates the solution.
Uncertainty principle gives a simple explanation. For a narrow barrier and high electric field across it, probability of finding the electron on the other side of the barrier takes a finite non-zero value.
True. But like most debates this got derailed into the finer details. As for complicating the subject keep in mind a lot of people have no clue what you or I are talking about. With that being said we might as well explore the smaller details.

Does considering splitting complicate things? Yeah but it COULD be an issue when getting down to 10nm as we were discussing (tunneling). The barrier will damn near be null at that point. As I said before it will be in the materials and design that will make or break a CPU when it gets that small. Intel has a tough road ahead IMO.
Posted on Reply
#23
hardcore_gamer
10nm is the channel length (physical), the thickness of the gate dielectric will be much less than that.Yes, Intel has a tough road ahead.

When the CMOS scaling hits a wall, all the major semiconductor companies should start making processors based on an open (license free) instruction set architecture which is more efficient than x86 and more scalable than ARM. ( my dream :D)
Posted on Reply
#24
ensabrenoir
just a matter of time

I'm of the belief that the time new tech hits the market those who put it out are r &d ing something 10 to 20 years beyound it. Consumer level is an inch above. End of life. We may not b able to see it like henery ford and his model t Couldn't see. The latest bmw 7 series but were on our way 2 nano tech just like the cartoons and movies. Our 2011 and bulldozers will b used in children toys and cofee makers(make u the perfect cup according to your dna)
Posted on Reply
#25
TheMailMan78
Big Member
hardcore_gamer said:
10nm is the channel length (physical), the thickness of the gate dielectric will be much less than that.Yes, Intel has a tough road ahead.

When the CMOS scaling hits a wall, all the major semiconductor companies should start making processors based on an open (license free) instruction set architecture which is more efficient than x86 and more scalable than ARM. ( my dream :D)
This could be your dream man.....

http://www.cbc.ca/news/technology/story/2008/01/21/algae-computers.html

Can't patient nature. :toast:
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