Wednesday, August 8th 2018

ATP Announces eMMC 5.1 Chips

Fueled by continuous big data generation, the ongoing industrial revolution requires storage solutions that offer not only high performance, but also uncompromising reliability and maximum endurance. ATP Electronics, a leading manufacturer of industrial memory and storage solutions, tackles these tough storage demands with its new industrial e.MMC product family.

The ATP industrial e.MMC, which adheres to JEDEC e.MMC v5.1 Standard (JESD84-B51), is poised to make its mark at the Flash Memory Summit 2018 in Santa Clara, USA from August 7 to 9, 2018.
Big Features in a Tiny Package
Constructed with 3D NAND flash and with densities of up to 128 GB, the ATP e.MMC has an industrial operating temperature rating (-40°C to 85°C) for exceptional thermal tolerance in extremely hot or cold environments. It comes in a 153-ball fine pitch ball grid array (FBGA) package that integrates a MultiMedia Card (MMC) interface, flash memory and controller within a single IC package that is smaller than a typical postage stamp. The integrated package allows the e.MMC to internally manage basic functions such as error correction, bad block management and wear leveling, thus freeing the host from having to perform low-level flash operations. Being soldered directly to the printed circuit board, the e.MMC is resistant against vibrations, ensuring reliable performance even during grueling operations. The compact package, ample capacity and low power consumption make the ATP e.MMC perfect for handling big data while taking up small space.

"This year's FMS theme, 'Designing for Big Data Demands' encapsulates ATP's goal to provide the most viable solutions for the tough requirements of diverse industrial applications," said Marco Mezger, ATP Vice President of Global Marketing. "We are very proud to introduce the new industrial e.MMC, which achieves unprecedented reliability and 2-3X the endurance of standard e.MMC solutions, thanks to the superior IC NAND flash characterization as well as intense testing and validation that ATP has always been known for."

The e.MMC v5.1 standard enables new features such as Command Queuing and Cache Barrier to enhance random read/write performance; Enhanced Strobe in HS400 Mode for faster synchronization between the host and the e.MMC device; Cache Flushing Report to ensure data integrity on cache blocks; and, Secure Write Protection to ensure that only trusted entities can protect or unprotect the e.MMC device. ATP e.MMC is backward compatible with previous e.MMC versions (v4.41/v4.5/v5.0).

Intelligent Management
To ensure the highest levels of performance, utmost reliability, better endurance, and product longevity, the ATP e.MMC employs smart solutions such as Advanced Global Wear Leveling and SSD-level low-density parity check error correction code (LDPC ECC) technology for increased endurance. AutoRefresh and Dynamic Data Refresh guard against read disturb errors while SRAM soft error detector technology monitors error bit levels during device operation to ensure data integrity; and, the Early Retirement technology prevents data loss from weak blocks.

The S.M.A.R.T. (Self-Monitoring, Analysis, and Reporting Technology) function monitors endurance and reliability attributes to prevent unexpected data loss when the flash memory nears or reaches its end life, so device replacement plans can be made ahead of time.
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2 Comments on ATP Announces eMMC 5.1 Chips

Dainty Moderator
btarunr said:
so device replacement plans can be made ahead of time.
odd, I've only ever seen e.mmc soldered to the board and generally only availible in cheap units. like the HP stream minis
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Solaris17 said:
odd, I've only ever seen e.mmc soldered to the board and generally only availible in cheap units. like the HP stream minis
Smartphones and tablets?
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