Tuesday, January 11th 2022
PCI-SIG Releases PCIe 6.0 Specification: 64 GT/s Per Lane
PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe ) standard, today announced the official release of the PCIe 6.0 specification, reaching 64 GT/s. PCI Express technology has served as the de facto interconnect of choice for nearly two decades. The PCIe 6.0 specification doubles the bandwidth and power efficiency of the PCIe 5.0 specification (32 GT/s), while providing low latency and reduced bandwidth overhead.
"PCI-SIG is pleased to announce the release of the PCIe 6.0 specification less than three years after the PCIe 5.0 specification," said Al Yanes, PCI-SIG Chairperson and President. "PCIe 6.0 technology is the cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data center, artificial intelligence/machine learning, HPC, automotive, IoT, and military/aerospace, while also protecting industry investments by maintaining backwards compatibility with all previous generations of PCIe technology."
PCIe 6.0 Specification Features
"There is a growing demand for ever-increasing performance in many segments in the data center such as high-performance computing and AI," said Ashish Nadkarni, Group Vice President, Infrastructure Systems, Platforms and Technologies Group, IDC. "Within three to five years the application landscape will look very different and companies will likely begin updating their roadmaps accordingly. The advancement of an established standard like PCIe 6.0 architecture will serve the industry well in establishing composable infrastructure for performance intensive computing use cases."
For more information, visit this page.
"PCI-SIG is pleased to announce the release of the PCIe 6.0 specification less than three years after the PCIe 5.0 specification," said Al Yanes, PCI-SIG Chairperson and President. "PCIe 6.0 technology is the cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data center, artificial intelligence/machine learning, HPC, automotive, IoT, and military/aerospace, while also protecting industry investments by maintaining backwards compatibility with all previous generations of PCIe technology."
- 64 GT/s raw data rate and up to 256 GB/s via x16 configuration
- Pulse Amplitude Modulation with 4 levels (PAM4) signaling and leverages existing PAM4 already available in the industry
- Lightweight Forward Error Correct (FEC) and Cyclic Redundancy Check (CRC) mitigate the bit error rate increase associated with PAM4 signaling
- Flit (flow control unit) based encoding supports PAM4 modulation and enables more than double the bandwidth gain
- Updated Packet layout used in Flit Mode to provide additional functionality and simplify processing
- Maintains backwards compatibility with all previous generations of PCIe technology
"There is a growing demand for ever-increasing performance in many segments in the data center such as high-performance computing and AI," said Ashish Nadkarni, Group Vice President, Infrastructure Systems, Platforms and Technologies Group, IDC. "Within three to five years the application landscape will look very different and companies will likely begin updating their roadmaps accordingly. The advancement of an established standard like PCIe 6.0 architecture will serve the industry well in establishing composable infrastructure for performance intensive computing use cases."
For more information, visit this page.
25 Comments on PCI-SIG Releases PCIe 6.0 Specification: 64 GT/s Per Lane
Every professional PCI 4.0 flash SSD already hits the sustained write wall well below it's peak rates after that cache is exhausted! And video cards still can't saturate PCIe 3.0 x16.
Servers can use it t add more devices, but with the insane price of video cards, supply is going to be hard to come by.
If you ever wonder why it is that game worlds aren't as interactive and dynamic as you'd expect them to be, this is one the reasons.
And the reason why game world aren't dynamic at all has more to do with developer time being prioritized on other content (you can't both make a seamless dynamic game, and also spend the same amount of time you used to do on creating characters + storyboard + models + licensed content . SO YOU END UP WITH A VERY EMPTY BUT DYNAMIC WORLD!)
Yes, the IO is still a limiting factor for creating these dynamic worlds, but users have already made their decision about how much they want their AAA game to be like a movie (AND WHEN WAS THE LAST TIME YOU SAW ONE OF THOSE SUCCESSFUL MOVIES BE INTERACTIVE?
Bring it
:)
On a side note, I wonder will we live to see commercial NVRAM with in-mem computing at the current DDR5 speeds?
If you look at Intel's chipsets for Alder Lake, they offer PCIe 5.0 from the CPU, PCIe 4.0 from the CPU, PCIe 4.0 from the chipset and PCIe 3.0 from the chipset.
This is likely to continue for quite some time, as not everything needs to be on PCIe 5.0, or even 4.0.
PCIe 3.0 is the last "simple" implementation of PCIe, as it doesn't require signal "boosters" of any kind, unlike later standards, so we're likely to continue to see it in lower cost platforms and various embedded systems for at least another five to 10 years. PCIe 4.0 is still quite manageable, but PCIe 5.0 is very expensive to implement once you have traces over a certain length as it requires signal retimers, rather than the much cheaper redrivers that PCIe 4.0 can use, even if it's not recommended by the PCIe SIG.Not likely, as things are starting to hit a lot of limits of current manufacturing technology.
There's work being done on optical connectivity to try and prevent signal degradation, but it's still a long way until we get to a sensible implementation of that.That was a node issue, but just as with CPUs, higher speeds have either required more cooling, or an improved production node.