Saturday, October 26th 2024
AMD Ryzen 7 9800X3D Has the CCD on Top of the 3D V-cache Die, Not Under it
Much of the Ryzen 7 9800X3D teaser material from AMD had the recurring buzzwords "X3D Reimagined," causing us to speculate what it could be. 9550pro, a reliable source with hardware leaks, says that AMD has redesigned the way the CPU complex die (CCD) and 3D V-cache die (L3D) are stacked together. In past generations of X3D processors, such as the 5800X3D "Vermeer-X" and the 7800X3D "Raphael-X," the L3D is stacked on top of the CCD. It would stack above the central region of the CCD that has the on-die 32 MB L3 cache, while blocks of structural silicon would be placed on top of the edges of the CCD that have the CPU cores, with these structural silicon blocks performing the crucial task of transferring heat from the CPU cores to the IHS above. This is about to change.
If the leaks are right, AMD has inverted the CCD-L3D stack with the 9000X3D series such that the "Zen 5" CCD is now on top, the L3D is below it, under the central region of the CCD. The CPU cores now dissipate heat to the IHS as they do on regular 9000 series processors without the 3D V-cache technology. The way we imagine they achieved this is by enlarging the L3D to align with the size of the CCD, and serve as a kind of "base tile." The L3D would have to be peppered with TSVs that connect the CCD to the fiberglass substrate below. We know where AMD is going with this in the future. Right now, the L3D "base tile" contains the 64 MB 3D V-cache that gets appended to the 32 MB on-die L3 cache, but in the future (probably with "Zen 6"), AMD could design the CCDs with TSVs even for the per-core L2 caches.
This piece of speculation also perfectly explains what "X3D boost" could be. With the CCD making direct contact with the IHS the way it is in non-X3D processors, the X3D processors could have the same overclocking capabilities as the regular chips. There are much fewer thermal hurdles in the way, and AMD can go ahead and give these chips the same TDP and PPT values as regular chips, as well as higher clock speeds. The company used to be conservative with the PPT and clock speeds of its X3D processors in the past.
AMD is expected to launch the Ryzen 7 9800X3D on November 7, 2024.
Source:
HXL (Twitter)
If the leaks are right, AMD has inverted the CCD-L3D stack with the 9000X3D series such that the "Zen 5" CCD is now on top, the L3D is below it, under the central region of the CCD. The CPU cores now dissipate heat to the IHS as they do on regular 9000 series processors without the 3D V-cache technology. The way we imagine they achieved this is by enlarging the L3D to align with the size of the CCD, and serve as a kind of "base tile." The L3D would have to be peppered with TSVs that connect the CCD to the fiberglass substrate below. We know where AMD is going with this in the future. Right now, the L3D "base tile" contains the 64 MB 3D V-cache that gets appended to the 32 MB on-die L3 cache, but in the future (probably with "Zen 6"), AMD could design the CCDs with TSVs even for the per-core L2 caches.
AMD is expected to launch the Ryzen 7 9800X3D on November 7, 2024.
110 Comments on AMD Ryzen 7 9800X3D Has the CCD on Top of the 3D V-cache Die, Not Under it
1. Much easier to cool the cores
2. This let AMD to increase the clock speed
3. They could use bigger cache chip/size?
4. That may make it easier to provide the 3D cache to all CCDs
I don't know how to categorise this, leak or rumour. But results seems good.
Another thing they could do with this is place their different CCD ZenCore types above or below the higher performant ZenCore type though it impacts the trace lengths a bit to the stacked cache below. Lastly they could put the higher performing ZenCore CCD above the stacked cache and lower performing, but more efficient ZenCore CCD below the stacked cache. That last option eliminates the trace lengths concern, but might be less ideal on thermals overall though probably better balanced to keep thermals of the higher performing ZenCore CCD higher. The bottom CCD would really just be there for efficiency and additional cores for higher multi-thread performance where needed.
I don't see them doing that right off, but if their trying to push things in the direction of 16c32t it's likely what they'll be considering.
My 5800XD ran quite a bit warmer than my 5950X in games by a good 15°C to 20°C, and this was on a 360mm AIO, and my 7950X3D actually runs cooler in games than the 5800X3D did but still warmer than the 5950X did.
There'are probably loads of things that makes this hard or complicated, but I have no idea if this is impossible.
On the other hand, what's taking so long with 9900X3D/9950X3D? Isn't it pretty much the same thing as last time? Maybe there's more difference between the generations than moving the cache after all?
256 MB sounds like diminishing returns to me.
The only way it might impact latency negatively is stacking a CCD on top of another CCD on top of X3D cache the top CCD in that scenario would have a bit longer trace lengths to the cache though it would be better located in terms of heat output. That theoretical would still be better than the current 7950X3D with the CCX latency issues though.
Having 2 cache chiplets on $700 - $750 parts is likewise absolutely possible.
Even if the uplift is a mere 3%, every little bit matters at the high end. Particularly when it could make the 9950X3D reach gaming parity with the 9800X3D, it would upsell a lot of people to the more expensive processor.
It's the slower clock speed that causes lower performance.
You are vastly under-estimating the number of people wanting a chip that can do both gaming and core heavy tasks. I for one would have purchased a 7950X3D if it had matched a 7800X in gaming and I might purchase a 9950X3D if it matches the 9800X3D in gaming performance. For people buying in this price bracket it's a no-brainer to spend a little bit more to get a system that can do it all.You are conflating things, X3D chips perform worse in certain applications that are frequency sensitive that don't benefit from cache. In core heavy workloads they are 100% equal to their non-X3D counterparts.
Mind you, if AMD stacks the CCD above the cache as the article implies they may do, that negative disappears.We know this is false because AMD themselves has stated X3D was designed for servers. That it came to consumer products is due to a side experiment by an AMD employee who wanted to see if there was benefit in everyday workloads.Read the article, it specifically states that AMD may be getting rid of these limiations.