Thursday, July 23rd 2026
AMD Announces 6th Gen EPYC Server Processors Powered by "Zen 6" Microarchitecture
AMD today announced the 6th Gen EPYC "Venice" server processors powered by the "Zen 6" CPU microarchitecture. The family includes a set of four distinct product lines, the EPYC 9006 (Socket SP7) for mainline servers with market leadership in core-counts and performance; the EPYC 9006 (Socket SP8) for enterprises with optimized performance per node; EPYC 9006X SP7 for high performance computing accelerated by larger CPU caches; and the EPYC 9006 LP "Verano" processors for AI host nodes powered by LPDDR memory.
The EPYC 9006 "Venice" family offers CPU core counts of up to 96-core/192-thread on chips with "Zen 6" cores, and up to 256-core/512-thread on chips with compacted "Zen 6c" cores. "Venice-X" HPC processors with 3D V-Cache offer up to 1,152 MB of L3 cache per socket. AMD has significantly upgraded the memory sub-system of these processors, giving Socket SP7 a 16-channel DDR5 memory interface with native support for DDR5-8000 RDIMMs, support for MRDIMMs with up to DDR5-12800 speeds. Specific variants also come with 24-channel LPDDR5X interfaces that support field-replaceable SOCAMM2 modules.
In terms of platform, EPYC "Venice" supports 1P and 2P socket configurations. Each socket puts out 128 PCI-Express Gen 6 lanes, with support for memory expansion via CXL 3.1 and 5th Gen Infinity Fabric. The company introduced several new power-management and QoS features for admins, including support for unified power provisioning (UPP), utilization-based power scaling (UBPS), and FAST (frequency-adaptive spectrum technology). AMD also introduced several new security features, both at the "Zen 6" microarchitecture-level, and specific to its server processors at the sIOD-level. These include enhanced RoT and RSA 4K encryption with PQC support; and mitigations for several new kinds of physical and side-channel attacks.
AMD EPYC "Venice" series is in production now, with the 9006 SP7 series shipping in Q4 2026, 9006 SP8 bound for the first half of 2027, the 9006X SP7 series HPC processors bound for the second half of 2027, along with the 9006 LP series.
Riding on IPC improvements of the "Zen 6" cores, wider 16-channel DDR5 memory interfaces, and faster DDR5-8000 memory, EPYC processors are shown offering significantly higher throughput and performance against contemporaries from Intel and Arm.
Performance Claims
The EPYC 9006 "Venice" family offers CPU core counts of up to 96-core/192-thread on chips with "Zen 6" cores, and up to 256-core/512-thread on chips with compacted "Zen 6c" cores. "Venice-X" HPC processors with 3D V-Cache offer up to 1,152 MB of L3 cache per socket. AMD has significantly upgraded the memory sub-system of these processors, giving Socket SP7 a 16-channel DDR5 memory interface with native support for DDR5-8000 RDIMMs, support for MRDIMMs with up to DDR5-12800 speeds. Specific variants also come with 24-channel LPDDR5X interfaces that support field-replaceable SOCAMM2 modules.
Performance Claims
- AMD frames Venice as extending five generations of EPYC leadership, quoting up to 18x the throughput of its 1st Gen "Naples" EPYC 7601. Against the competition (all AMD-measured or -estimated):
- vs. NVIDIA Vera (88C): Up to 2.2x the throughput on SPECrate 2026_int_base (256C/600 W), 1.2x higher per-core performance (96C HF), and up to 2.8x agents per watt. AMD also claims a "Venice"-powered rack delivers up to 2.2x the cores of a Vera-powered rack.
- vs. Intel Xeon 6980P (128C): Up to 1.3x higher per-core performance and up to 3.3x performance in sandbox scenarios.
- vs. Arm AGI (136C): Up to 2.0x the throughput on SPECrate 2017_int_base.
- Cloud-native: Up to 2.6x-3.7x on MongoDB, Redis, NGINX and MySQL versus 6th Gen Intel Xeon.
- HPC: Up to 3.1x on GROMACS, NAMD, Quantum Espresso and WRF.
- Host node: 1.8x higher tokens/s for frontier models versus 5th Gen EPYC "Turin," thanks to PCIe Gen 6 doubling CPU-to-GPU bandwidth.
- Consolidation: AMD claims 1000 aging 2P Intel Xeon Gold 6258R servers can be replaced by just 82 2P EPYC 9996 servers—up to 92% fewer servers, up to 77% less power, and up to 40% lower 5-year TCO.
18 Comments on AMD Announces 6th Gen EPYC Server Processors Powered by "Zen 6" Microarchitecture
The DDR4 standard specifies one 64-bit channel per DIMM.
The DDR5 standard specifies 2 independent 32-bit sub-channels per DIMM. Thus, in dual-channel configuration (two memory sticks) DDR5 has 4 32-bit sub-channels.
Each sub-channel in DDR5-6400 is running at twice the frequency of DDR4-3200 - this explains why DDR5-6400 achieves twice the bandwidth of DDR4-3200.
DDR5 latency is the same as DDR4 latency.
DDR4 and DDR5 have the same minimum access size: 64 bytes. DDR4: 8*8 bytes (8*64 bits). DDR5: 16*4 bytes (16*32 bits).
DDR4 and DDR5 have the same number of pins per DIMM: 288.
DDR6 is expected to have 4 24-bit sub-channels per DIMM, which implies that it will have to have a larger number of pins than DDR4/DDR5 - which implies that the AM6 socket (which might support DDR6) will have to have a correspondingly larger number of pins than the AM5 socket.
DDR6 specification hasn't been published yet.
In summary: Dual-channel DDR5 performs like a true quad-channel DDR4, and dual-channel DDR6 can be expected to perform like a true hexa-channel DDR4 because (4*24*12800)/(64*3200) = 6.
This seems to be the most confusing part of their presentation.
1. SP7 - three highest SKUs show x96 lanes and all other SKUs from 128 cores and below show x128 lanes
2. SP8 - all processors on AMD website show 128 lanes, so this seems clear
3. on 2P platforms for SP7 and SP8, AMD did not show any lane count, or at least I have not seen any slide explicitly addressing 2P, despite some tech media floating the number 160 lanes
Hyperscalers have taken care of their RAM purchases. Don't you worry about them.
There isn't a neutral institution that defines a "normal" RAM price.
When supply is extraordinarily concentrated (only 3 or 4 relevant producers of RAM worldwide), the suppliers themselves have considerable ability to shape the supply curve that determines that price.
In the major 1999–2002 DRAM cartel case, Samsung, Hynix, Infineon and Elpida pleaded guilty or were prosecuted for coordinating DRAM prices.
- They can deliberately constrain production
- They control the timing of new capacity
- They can allocate wafers between products
- They can retire old production capacity
- They can also exploit the enormous fixed-cost structure of fabs
- They can influence the "reference price"
- They have unusually good information about their competitors
All in all this oligopoly gives them much control over the supply curve from which the market price emerges.
From those facts alone, a "normal" RAM price from your perspective (like 100 USD for a 32GB DDR5 Kit) may be totally different from the perspective of the RAM Producers. They may want to see the "normal" Price of that around 600 USD, instead of 100 USD.
Maybe we have normal RAM prices right now. Maybe we still are away from normal RAM prices, and they want to establish an even higher price to be "the new normal" RAM price.
It won't happen today or this year but eventually DRAM prices will drop, and likely drop further than they were in 2025. The market demands DRAM and someone will supply.
“I think the fact that everything is scarce is fantastic for us.” - Jensen Huang CEO NVIDIA