Friday, July 24th 2026
Intel Reaffirms: Multithreading Returns in 2028 with "Coral Rapids"
In recent years, Intel has shifted away from traditional multithreading in its CPU core designs. This change began with the 12th-Gen Core CPUs when Intel started moving away from Hyper-Threading. At the same time, the company transitioned to asymmetrical CPU designs, initially enabling SMT only on performance cores. On the consumer side, Intel completely abandoned Hyper-Threading with the Core Ultra 200 series but still maintains it in the P-Core Xeon 6 "Granite Rapids" CPU family, which features up to 128 P-Cores and 256 threads. Meanwhile, the "Clearwater Forest" E-Core Xeon 6 has 288 E-Cores without Hyper-Threading, and Intel's upcoming Xeon 7 "Diamond Rapids" P-Core SKUs will have 192 cores and 192 threads, meaning no Hyper-Threading. Intel plans to address this by reintroducing Hyper-Threading the following year with the Xeon 8 "Coral Rapids."
The no-SMT Xeon 7 "Diamond Rapids" is expected in 2027, but 2028 is when SMT is set to make a big comeback. This timing coincides with Intel's 14A node high-volume manufacturing, meaning "Coral Rapids" could utilize the 14A node for its compute tile. With advancements in yield, advanced packaging, and more under Intel's Foundry division, we anticipate a capable lineup in the coming years.
Source:
Intel Earnings Call Transcript
Intel CEO Lip-Bu TanWe have Clearwater Forest, Diamond Rapids, and also Coral Rapids with the SMT involved. I think we continue working on improving the competitiveness against our competitor. I think clearly it's very important to drive the improvement in the single thread and also multithreading. Multithreading will be coming in the Coral Rapids.
37 Comments on Intel Reaffirms: Multithreading Returns in 2028 with "Coral Rapids"
Why not try ultrathreading and go for four threads per core. What could possibly go wrong?
I could be wrong though
How could that possibly be sarcasm?
In addition the cache starvation issues, SMT gave rise to the Spectre and Meltdown list of CVEs and all the variants like Downfall, Foreshadow, Zombieload etc. Sharing information from two different threads in the same physical registers is really hard to do in a way that is 100% unexploitable, without also reducing the effectiveness of SMT's performance to the point that it's worse than disabling SMT entirely. Doubling it to four threads is basically idiotic outside of controlled, secured environments.
Only reason this is coming back is so smaller chips can be sold with similar MT perf.
Zen6 EPYC is stomping on everything under the Sun and increasing the catch-up distance.
I just have no idea what core they will be using for Coral Rapids. Maybe a Griffin Cove-X?
A bad choice to introduce hyperthreading. It implies intel does not help in optimising the existing scheduler for their proprietary cpu design. Hyperthreading should not give any performance boost when the software is written correctly and the hardware was designed well with the software in mind.
What's the minimum now 5 or 6 cores? for budget CPU's?
i doubt i have ever seen any 5 core desktop amd64 based cpu.
AMD hasn't made anything budget friendly in ages.
In our testing, loading the second thread adds roughly 12% on a Skylake-era Xeon (with default side channel mitigations active), 23-25% on Sapphire Rapids, 29-32% on Xeon 6, and 32-33% on Zen 5
To avoid duplicate engineering efforts the performance cores in consumer CPUs are essentially the same as in servers. Although it's well known people don't need more then 640KB RAM or computers at all, it makes no sense to throw an easy 30 percent performance increase away.
IBM is not x86 so some of its custorers workloads can indeed leverage SMT8.
Nvidias little different approarch with Vera is interesting too, but again not x86.
Beside those things intel changed its trajectories a few times in the recent years and must have been rotating quiet fast since Keller dropped the mic.
edit (addition): Intels biggest obvious problem is still their non existent answer to AMDs scaleable-fabric, wich again evolved with CDNA5 wich dropped the Infinity-cache and went for bigger L2.
Intel still lags something like that in server and consumer space ... yet. Maybe the SMToff, SMTon is the visible part of that in some way.
This is hopefully obvious sarcasm.
ISA has nothing to do with how well SMT scales. SMT is purely a backend feature and the ISA doesn't matter by that point.
Zen 5 is the only AMD Zen generation I think that didn't see a Fmax bump in DT, but in server tons of chips saw single core boost bumps.
What's interesting too is the distinction of 'single core frequency/boost' in client vs server. AFAIK, in client, only select cores have to boost up to "x" GHz for "x" GHz to be the boost clock. For server (for AMD at least), single core boost has to be achievable by any core in the chip.Lion Cove is a huge architectural shift vs GLC, even if the IPC figures did not really back it up. Similar with Zen 5 actually, another large architectural shift, not much IPC gain in specint2017 at least.Venice has 33% more cores, SMT, and uses a better node.
DMR will have some of it's own advantages (hybrid bonding L3, fewer chiplets also wastes less power, but I doubt it's enough to overcome the advantages Venice has.That's my assumption as well.I don't think all 96 cores will be boosting at 5GHz, just that any one of the cores can boost at that clock.