AMD today unveiled its next-generation Ryzen 7000 desktop processors, based on the Socket AM5 desktop platform. The new Ryzen 7000 series processors introduce the new "Zen 4" microarchitecture, with the company claiming a 15% single-threaded uplift over "Zen 3" (16-core/32-thread Zen 4 processor prototype compared to a Ryzen 9 5950X). Other key specs about the architecture put out by AMD include a doubling in per-core L2 cache to 1 MB, up from 512 KB on all older versions of "Zen." The Ryzen 7000 desktop CPUs will boost to frequencies above 5.5 GHz. Based on the way AMD has worded their claims, it seems that the "+15%" number includes IPC gains, plus gains from higher clocks, plus what the DDR4 to DDR5 transition achieves. With Zen 4, AMD is introducing a new instruction set for AI compute acceleration. The transition to the LGA1718 Socket AM5 allows AMD to use next-generation I/O, including DDR5 memory, and PCI-Express Gen 5, both for the graphics card, and the M.2 NVMe slot attached to the CPU socket.

Much like Ryzen 3000 "Matisse," and Ryzen 5000 "Vermeer," the Ryzen 7000 "Raphael" desktop processor is a multi-chip module with up to two "Zen 4" CCDs (CPU core dies), and one I/O controller die. The CCDs are built on the 5 nm silicon fabrication process, while the I/O die is built on the 6 nm process, a significant upgrade from previous-generation I/O dies that were built on 12 nm. The leap to 5 nm for the CCD enables AMD to cram up to 16 "Zen 4" cores per socket, all of which are "performance" cores. The "Zen 4" CPU core is larger, on account of more number-crunching machinery to achieve the IPC increase and new instruction-sets, as well as the larger per-core L2 cache. The cIOD packs a pleasant surprise—an iGPU based on the RDNA2 graphics architecture! Now most Ryzen 7000 processors will pack integrated graphics, just like Intel Core desktop processors.

AMD is planning a massive integrated graphics performance uplift for its next-generation Ryzen 7000U mobile processors. Codenamed "Phoenix," this SoC will feature a CPU based on the "Zen 4" microarchitecture with a higher CPU core count than the Intel alternative of the time; and an iGPU based on the RDNA3 graphics architecture. AMD is planning to endow this with the right combination of a CU count and engine clocks, to result in performance that roughly matches the NVIDIA GeForce RTX 3060 Laptop GPU, a popular performance-segment discrete GPU for notebooks, according to greymon55. Other highlights of "Phoenix" include a DDR5 + LPDDR5 memory interface, and PCI-Express Gen 5. The SoC is expected to be built on the TSMC N5 (5 nm) process, and debut in 2023.

A technological race is brewing between NVIDIA and AMD over which brand's GPU reaches the 100 TFLOP/s peak FP32 throughput mark first. AMD's TeraScale graphics architecture and the "RV770" silicon, were the first to hit the 1 TFLOP/s mark, way back in 2008. It would take 14 years for this figure to reach 100 TFLOP/s for flagship GPUs. NVIDIA's next generation big GPU based on the "Ada Lovelace," the AD102, is the green team's contender for the 100 TFLOP/s mark, according to kopite7kimi. To achieve this, all 144 streaming multiprocessors (SM) or 18,432 CUDA cores, of the AD102 will have to be enabled.

From the red team, the biggest GPU based on the next-generation RDNA3 graphics architecture, "Navi 31," could offer peak FP32 throughput of 92 TFLOP/s according to greymon55, which gives AMD the freedom to create special SKUs running at high engine clocks, just to reach the 100 TFLOP/s mark. The Navi 31 silicon is expected to triple the compute unit count over its predecessor, resulting in 15,360 stream processors. Both the AD102 and Navi 31 are expected to be built on the same TSMC N5 (5 nm EUV) node, and product launches for both are expected by year-end.

Despite rumours of both production issues and node delays, Samsung has assured its shareholders during its first quarter conference call, that the company is on track. Its yield rate from its 5 nm node was said to have entered maturity, meaning that yields have entered Samsung's expected levels. However, Samsung did admit that its 4 nm node had seen some delays with the ramp up, but it has now entered the expected yield rate curve. The company is also working on an new R&D line for its upcoming 3 nm node, but didn't go into any further details.

As for Samsung's DRAM products, there were rumours that its 12 nm 1b process node had hit some snags and that the company was going to skip ahead to its 1c node, something the company denied. Samsung added that the development of 1b was proceeding stably and that the 1c node is expected to be done on schedule. The company also said that media reports of issues at Samsung's foundry business were overblown and that order books are full, which is why some of its customers have had to produce additional parts with TSMC. Samsung's foundry business reportedly saw an increase in operating profit of 50 percent compared to last year, as well as an increase in revenue of 19 percent.

AMD's next-generation MI300 compute accelerator is expected to significantly scale up the logic density, according to a rumor by Moore's Law is Dead. Based on the CDNA3 compute architecture, the MI300 will be a monstrous large multi-chip module with as many as 8 logic dies (compute dies), each with its dedicated HBM3 stack. The compute dies (logic dies), will be 3D-stacked on top of I/O dies that pack the memory controllers, and the interconnect that performs the inter-die, and inter-package communication.

The report even goes on to mention that the compute die at the top level of the stack will be built on TSMC N5 (5 nm) silicon fabrication process, while the I/O die below will be TSMC N6 (6 nm). At this point it's not known if AMD will use the package to wire the logic stacks to the memory stacks, or whether it will take the pricier route of using a silicon interposer, but the report supports the interposer theory—that an all-encompassing interposer seats all eight compute dies, all four I/O dies (each with two compute dies), and the eight HBM3 stacks. An interposer is a silicon die that facilitates high density microscopic wiring between two dies on a package, which are otherwise not possible through large package substrate wiring.

Addressing increasing performance requirements for artificial intelligence (AI) systems on chip (SoCs), Synopsys, Inc. today announced its new neural processing unit (NPU) IP and toolchain that delivers the industry's highest performance and support for the latest, most complex neural network models. Synopsys DesignWare ARC NPX6 and NPX6FS NPU IP address the demands of real-time compute with ultra-low power consumption for AI applications. To accelerate application software development for the ARC NPX6 NPU IP, the new DesignWare ARC MetaWare MX Development Toolkit provides a comprehensive compilation environment with automatic neural network algorithm partitioning to maximize resource utilization.

"Based on our seamless experience integrating the Synopsys DesignWare ARC EV Processor IP into our successful NU4000 multi-core SoC, we have selected the new ARC NPX6 NPU IP to further strengthen the AI processing capabilities and efficiency of our products when executing the latest neural network models," said Dor Zepeniuk, CTO at Inuitive, a designer of powerful 3D and vision processors for advanced robotics, drones, augmented reality/virtual reality (AR/VR) devices and other edge AI and embedded vision applications. "In addition, the easy-to-use ARC MetaWare tools help us take maximum advantage of the processor hardware resources, ultimately helping us to meet our performance and time-to-market targets."

One of the largest cloud providers in China, Alibaba, has today announced a preview for a new instance powered by Yitian 710 processor. The new processor is a collection of Alibaba's efforts to develop a home-grown design capable of powering cloud instances and the infrastructure needed for it and its clients. Without much further ado, the Yitian 710 is based on Armv9 ISA and features 128 cores. Ramping up to 3.2 GHz, these cores are paired with eight-channel DDR5 memory to enable sufficient data transfer. In addition, the CPU supports 96 PCIe 5.0 lanes for IO with storage and accelerators. These are most likely custom designs, and we don't know if they are using a blueprint based on Arm's Neoverse. The CPU is manufactured at TSMC's facilities on 5 nm node and features 60 billion transistors.

Alibaba offers these processors as a part of their Elastic Compute Service (ECS) instance called g8m, where users can select 1/2/4/8/16/32/64/128 vCPUs, where each vCPU is equal to one CPU core physically. Alibaba is running this as a trial option and notes that users should not run production code on these instances, as they will disappear after two months. Only 100 instances are available for now, and they are based in Alibaba's Hangzhou zone in China. The company notes that instances based on Yitian 710 processors offer 100 percent higher efficiency than existing AMD/Intel solutions; however, they don't have any useful data to back it up. The Chinese cloud giant is likely trying to test and see if the home-grown hardware can satisfy the needs of its clients so that they can continue the path to self-sustainability.

Here is the first picture of a next-generation AMD EPYC "Genoa" processor with its integrated heatspreader (IHS) removed. This is also possibly the first picture of a "Zen 4" CPU Complex Die (CCD). The picture reveals as many as twelve CCDs, and a large sIOD silicon. The "Zen 4" CCDs, built on the TSMC N5 (5 nm EUV) process, look visibly similar in size to the "Zen 3" CCDs built on the N7 (7 nm) process, which means the CCD's transistor count could be significantly higher, given the transistor-density gained from the 5 nm node. Besides more number-crunching machinery on the CPU core, we're hearing that AMD will increase cache sizes, particularly the dedicated L2 cache size, which is expected to be 1 MB per core, doubling from the previous generations of the "Zen" microarchitecture.

Each "Zen 4" CCD is reported to be about 8 mm² smaller in die-area than the "Zen 3" CCD, or about 10% smaller. What's interesting, though, is that the sIOD (server I/O die) is smaller in size, too, estimated to measure 397 mm², compared to the 416 mm² of the "Rome" and "Milan" sIOD. This is good reason to believe that AMD has switched over to a newer foundry process, such as the TSMC N7 (7 nm), to build the sIOD. The current-gen sIOD is built on Global Foundries 12LPP (12 nm). Supporting this theory is the fact that the "Genoa" sIOD has a 50% wider memory I/O (12-channel DDR5), 50% more IFOP ports (Infinity Fabric over package) to interconnect with the CCDs, and the mere fact that PCI-Express 5.0 and DDR5 switching fabric and SerDes (serializer/deserializers), may have higher TDP; which together compel AMD to use a smaller node such as 7 nm, for the sIOD. AMD is expected to debut the EPYC "Genoa" enterprise processors in the second half of 2022.

According to DigiTimes, TSMC is working on increased its monthly shipments of finished wafers from 120,000 to 150,000 for its 5 nm nodes, under which 4 nm also falls. This is three times as much as what TSMC was producing just a year ago. The 4 nm node is said to be in full mass production now and the enhanced N4P node should be ready for mass production in the second half of 2022, alongside N3B. This will be followed by the N4X and N3E nodes in 2023. The N3B node is expected to hit 40-50,000 wafers initially, before ramping up from there, assuming everything is on track.

The report also mentions that TSMC is expecting a 20 percent revenue increase from its 28 to 7 nm nodes this year, which shows that even these older nodes are being heavily utilised by its customers. TSMC has what NVIDIA would call a demand problem, as the company simply can't meet demand at the moment, with customers lining up to be able to get a share of any additional production capacity. NVIDIA is said to have paid TSMC at least US$10 billion in advance to secure manufacturing capacity for its upcoming products, both for consumer and enterprise products. TSMC's top three HPC customers are also said to have pre-booked capacity on the upcoming 3 and 2 nm nodes, so it doesn't look like demand is going to ease up anytime soon.

Here's the first picture of an NVIDIA H100 "Hopper" compute processor, which succeeds the two-year old "Ampere" A100. The "Hopper" compute architecture doubles down on the strengths of "Ampere," in having the most advanced AI deep-learning compute machinery, FP64 math capability, and lots more. Built on the TSMC N5 (5 nm) node, the "GH100" processor more than doubles the transistor-count over the A100, which is expected to be around 140 billion.

Unlike the A100, the H100 will come with graphics rendering capability, The GH100 is one of the first NVIDIA chips to feature two different kinds of GPCs. Of the six GPCs has NVIDIA's graphics-relevant SMs, whereas the other GPCs have compute-relevant SMs. The graphics SM will have components such as RT cores, and other raster machinery; while the compute SMs will have specialized tensor cores and FP64 SIMD units. Counting the graphics SM, there are a total of 144 SMs on the silicon. Memory is care of what could be a 6144-bit HBM3 interface. NVIDIA will build various products based on the "GH100," including SXM cards, DGX Stations, SuperPods, and even PCIe add-in cards (AICs). NVIDIA is expected to unveil the H100 later today.

The output value of the world's top 10 foundries in 4Q21 reached US$29.55 billion, or 8.3% growth QoQ, according to TrendForce's research. This is due to the interaction of two major factors. One is limited growth in overall production capacity. At present, the shortage of certain components for TVs and laptops has eased but there are other peripheral materials derived from mature process such as PMIC, Wi-Fi, and MCU that are still in short supply, precipitating continued fully loaded foundry capacity. Second is rising average selling price (ASP). In the fourth quarter, more expensive wafers were produced in succession led by TSMC and foundries continued to adjust their product mix to increase ASP. In terms of changes in this quarter's top 10 ranking, Nexchip overtook incumbent DB Hitek to clinch 10th place.

TrendForce believes that the output value of the world's top ten foundries will maintain a growth trend in 1Q22 but appreciation in ASP will still be the primary driver of said growth. However, since there are fewer first quarter working days in the Greater China Area due to the Lunar New Year holiday and this is the time when some foundries schedule an annual maintenance period, 1Q22 growth rate will be down slightly compared to 4Q21.

Samsung Electronics is hit by a major scandal involving current and former employees. It's being alleged that these employees are involved in falsifying information about the semiconductor fabrication yields of the company's 3/4/5 nanometer nodes to clear them for commercial activity. This came to light when Samsung was observing lower than expected yields after the nodes were approved for mass-production of logic chips for Samsung, as well as third-party chip-designers. A falsified yield figure can have a cascading impact across the supply-chain, as wafer orders and pricing are decided on the basis of yields. Samsung however, has downplayed the severity of the matter. The group has initiated an investigation into Samsung Device Solutions, the business responsible for the foundry arm of the company. This includes a thorough financial audit of the foundry to investigate if the investments made to improve yields were properly used.

Intel's upcoming "Meteor Lake" and "Arrow Lake" client mobile processors introduce an interesting twist to the chiplet concept. Earlier represented in vague-looking IP blocks, new artistic impressions of the chip put out by Intel shed light on a 3-die approach not unlike the Ryzen "Vermeer" MCM that has up to two CPU core dies (CCDs) talking to a cIOD (client IO die), which handles all the SoC connectivity; Intel's design has one major difference, and that's integrated graphics. Apparently, Intel's MCM uses a GPU die sitting next to the CPU core die, and the I/O (SoC) die. Intel likes to call its chiplets "tiles," and so we'll go with that.

The Graphics tile, CPU tile, and the SoC or I/O tile, are built on three different silicon fabrication process nodes based on the degree of need for the newer process node. The nodes used are Intel 4 (optically 7 nm EUV, but with characteristics of a 5 nm-class node); Intel 20A (characteristics of 2 nm), and external TSMC N3 (3 nm) node. At this point we don't know which tile gets what. From the looks of it, the CPU tile has a hybrid CPU core architecture made up of "Redwood Cove" P-cores, and "Crestmont" E-core clusters.

AMD's final refresh of the RDNA2 graphics architecture, the Radeon RX 6x50 series, could debut in June or July 2022, according to Greymon55, a reliable source with GPU leaks. The final refresh of RDNA2 could see AMD use faster 18 Gbps GDDR6 memory across the board, and eke out higher engine clocks on existing silicon IP. At this point it's not known if these new chips will be built on the same 7 nm process, or are an optical shrink to 6 nm (TSMC N6). Such a shrink to a node that offers 18% higher transistor density, would have significant payoffs with clock-speed headroom. AMD's RDNA3-based 5 nm GPUs could debut only toward the end of the year.

In related news, AMD is preparing to launch another entry-level SKU within the RX 6000 series; the Radeon RX 6500 (non-XT). Based on the same 6 nm Navi 24 silicon as the RX 6500 XT, this SKU could have a core-configuration that's in-between the RX 6500 XT and the RX 6400, in featuring 768 stream processors across 12 compute units; and 4 GB of GDDR6 memory, which is similar to the RX 6400, but with higher engine clocks. The RX 6500 is targeting a $150 (MSRP) price-point.

Renowned hardware leaker kopike7kimi on Twitter revealed some purported details on NVIDIA's next-generation architecture for HPC (High Performance Computing), Hopper. According to the leaker, Hopper is still sporting a classic monolithic die design despite previous rumors, and it appears that NVIDIA's performance targets have led to the creation of a monstrous, ~1000 mm² die package for the GH100 chip, which usually maxes out the complexity and performance that can be achieved on a particular manufacturing process. This is despite the fact that Hopper is also rumored to be manufactured under TSMC's 5 nm technology, thus achieving higher transistor density and power efficiency compared to the 8 nm Samsung process that NVIDIA is currently contracting. At the very least, it means that the final die will be bigger than the already enormous 826 mm² of NVIDIA's GA100.

If this is indeed the case and NVIDIA isn't deploying a MCM (Multi-Chip Module) design on Hopper, which is designed for a market with increased profit margins, it likely means that less profitable consumer-oriented products from NVIDIA won't be featuring the technology either. MCM designs also make more sense in NVIDIA's HPC products, as they would enable higher theoretical performance when scaling - exactly what that market demands. Of course, NVIDIA could be looking to develop an MCM version of the GH100 still; but if that were to happen, the company could be looking to pair two of these chips together as another HPC product (rumored GH-102). ~2,000 mm² in a single GPU package, paired with increased density and architectural improvements might actually be what NVIDIA requires to achieve the 3x performance jump from the Ampere-based A100 the company is reportedly targeting.

TSMC has held its quarterly earnings conference today and it's good news all around, at least if you're TSMC or one of its shareholders, as the company reported record profits of US$6.01 billion for the quarter, or an increase of 16.4 percent compared to the same quarter last year. At the same time, the company announced that it's going to increase its CapEx, by no less than US$40-44 billion this year, which should be compared to the US$30 billion in 2021. The company is expecting to continue to rake in money this quarter, with an expected revenue before expenditures and tax of US$16.6 to US$17.2 billion, compared to US$15.74 billion for this quarter.

Looking at the graphs provided by TSMC which shows where its revenue is coming from, its 7 nm and 5 nm nodes are now accounting for 50 percent of TSMC's revenues. The 5 nm node on its own, almost made as much money as its 16 and 28 nm nodes combined in Q4. We can also see that the 5 nm has gone from eight percent of TSMC's revenues in 2020, to 19 percent this year, with the 7 nm node dropping slightly from 33 percent to 31 percent. 2021 saw a massive 51 percent revenue growth in automotive components for TSMC compared to 2020, yet it only accounted for four percent of TSMC's total revenue for 2021. Smartphones and HPC are jointly holding 81 percent of TSMC's business based on revenue, which isn't likely to change any time soon.

Anandtech asked AMD during a meeting at CES about the production nodes used to make its chips at TSMC and the importance of leading edge nodes for AMD to stay competitive, especially in light of the cost of using said nodes. Lisa Su confirmed in her answer to Anandtech that AMD is using an optimised high-performance 5 nm node for its upcoming Zen 4 processor chiplets, which there interestingly appears to be both 2D and 3D versions of. This is the first time we've heard a mention of two different chiplet types using the same architecture and it could mean that we get to see Zen 4 based CPUs with and without 3D cache.

What strikes us as a bit odd about the Anandtech article, is that they mention the fact that several of TSMC's customers are already making 4 nm and soon 3 nm chips and are questioning why AMD wouldn't want to be on these same nodes. It seems like Anandtech has forgotten that not all process nodes are universally applicable and just because you can make one type of chip on a smaller node, doesn't mean it'll be suitable for a different type of chip. For the longest of times, mobile SoCs or other similar chips seem to always have been among the first things being made on new nodes, with more complex things like GPUs and more advanced CPUs coming later, to tweaked versions of the specific node. The fact that TSMC has no less than three 7 nm nodes, should be reason enough to realise that the leading edge node might not be the ideal node for all types of chips.

ASML, makers of vital semiconductor fabrication machinery powering the world's leading fabs, including TSMC, provided its first damage-assessment of the fire incident at one of its component plants near Berlin, on January 3. This plant manufactures several mechanical and optical components of semiconductor fabrication machinery, such as wafer tables and clamps, reticle chucks and mirror blocks.

ASML, in a press-release, disclosed that production of components used in DUV (deep-ultraviolet) machines, has been restarted, as that area of the plant is unaffected by the fire. A region of the plant that manufactures wafer clamps for use in its EUV (extreme ultraviolet) machines, however, has been affected by the fire. The company is still in the process of coming up with a recovery plan for this area, and will come up with a tentative date for restart of production only after that. EUV lithography is leveraged for 5 nm and upcoming 3 nm silicon fabrication nodes at TSMC, Samsung, and Intel. TSMC is known to be ASML's largest customer. ASML stated that it will release its Q4-2021 and full-year 2021 financial results on January 19, and it may provide more updates on the matter.The press-release follows.

AMD already declared the CPU core counts of its EPYC "Genoa" and "Bergamo" processors to top out at 96 and 128, respectively, a core-count believed to have been facilitated by the larger fiberglass substrate of the next-gen SP5 CPU socket, letting AMD add more 8-core "Zen 4" chiplets, dubbed CPU complex dies (CCDs). Until now, AMD has used the chiplet as a common component between its EPYC enterprise and Ryzen desktop processors, to differentiate CPU core counts.

A fascinating theory that hit the rumor-mill, indicates that the company might leverage 5 nm (TSMC N5) carve out larger CCDs with up to 16 "Zen 4" CPU cores. Half of these cores are capped at a much lower power budget, essentially making them efficient-cores. This is a concept AMD appears to be carrying over from its 15-Watt class mobile processors, which see the CPU cores operate under an aggressive power-management. These cores still turn out a reasonable amount of performance, and are functionally identical to the ones on 105 W desktop processors with a relaxed power budget.

AMD's next-generation Ryzen "Raphael" processor could launch only in the second half of 2022, confirms a leaked company slide scored by VideoCardz. The slide points to a Ryzen 5000X3D series product-stack update within the 1H-2022. These are Socket AM4 processors that leverage the company's updated "Zen 3(+)" CPU core die (CCD), which features 64 MB of 3D Vertical cache memory in addition to 32 MB of L3. AMD claims that 3DV Cache technology significantly improves performance akin to a generational update (anywhere between 5% to 25% depending on the application). The company is targeting "Spring" 2022 for launch, which would put this around early-Q2.

The "Raphael" Socket AM5 processor is sure to catch much of the attention, as it's the company's true next-gen desktop product. It heralds Socket AM5, a new LGA-based socket; and next-generation connectivity that includes DDR5 memory and PCI-Express Gen 5. The CCDs of these processors are built on the TSMC N5 (5 nm) silicon fabrication node, and are based on the "Zen 4" microarchitecture. The leaked slide shows the first grainy picture of Socket AM5, with a retention mechanism not unlike what we're used to, on the Intel platform. We're hearing rumors that AM5 will somehow manage cooler-compatibility with AM4 despite the radical redesign to the socket. An H2-2022 launch would put "Raphael" close to Intel's 13th Gen Core "Raptor Lake" launch, as team blue hopes to return to an annual IPC-uplift cadence, with up to 8 "Raptor Cove" P-cores, and 16 "Gracemont" E-cores.

According to an article by DigiTimes, which kind of states the obvious, the foundry industry isn't likely to change much over the next few years, as the cost of building a cutting edge foundry keeps increasing, which means the competition isn't likely to catch up with the market leaders. The costs mentioned are estimates, but seem quite likely and explains why there's so little competition in the foundry business.

It's unclear if the costs have been inflation adjusted or not, but a 90 nm 12-inch fab that could output 50,000 wafers a month, is said to have cost US$2.4 billion to build when it was the cutting edge node. Once things moved on to 28 nm, the equivalent fab would've cost US$6 billion, whereas a cutting edge 5 nm fab today, comes in at as much as US$16 billion. These are obviously long term investments, as even today, 90 nm nodes are used for plenty of chips, but most of the nodes above 28 nm are today used for specialty products rather than commonly used ICs, unless we're talking about 8-bit microcontrollers or some simpler components which companies such as TSMC and Samsung wouldn't even bother making.

China's technology reliance on 3rd party companies seems to be getting smaller. One of the leading technology companies in China, Huawei, has designed a laptop powered by a custom 5 nm Kirin SoC with DDR5 memory. Called the Dyna Cloud L420, Huawei has prepared this model for the Chinese market to provide a fully functional laptop that will get the job done, with no risk of the potential security backdoors implemented in the processor. Powered by a brand new Kirin 9006C SoC manufactured on TSMC's 5 nm process, it features eight unknown cores running at 3.1 GHz frequency. We assume that those are custom cores designed by Huawei. This SoC is accompanied by 8 GB of LPDDR5 memory, with 256 GB and 512 GB UFS 3.1 configurations storage options.

When it comes to the rest of the laptop, it rocks a 14-inch 2160x1440 display. I/O options are solid as well, as this machine has an HDMI video output, two USB-A, one USB-C, and Gigabit Ethernet using a mini-RJ45 port. Connectivity is provided by Wi-Fi 6 and Bluetooth 4.2. There is a 56 W/h battery that provides the juice to keep it running when it comes to the battery. And to complete all of that, this laptop officially only supports Huawei's proprietary Kirin OS (KOS) and Unity OS (UOS), with expected support for HarmonyOS in the future. Pricing and availability information is a mistery at the present date.

During the annual Snapdragon Tech Summit, Qualcomm Technologies, Inc. expanded the portfolio of solutions for Always On, Always Connected PCs with the introduction of the Snapdragon 8cx Gen 3 compute platform, designed to deliver the performance and exceptional experiences users deserve in premium ultra-slim and fanless laptops. To strengthen the entry-tier Windows PC and Chromebook ecosystems with robust 5G connectivity and advanced AI experiences, the Company also unveiled the Snapdragon 7c+ Gen 3 Compute Platform. Both platforms utilize smart, connected technology to modernize PC experiences and redefine mobile computing for end users.

"Snapdragon 8cx Gen 3 builds on the technology that has transformed the PC industry, delivering premium experiences with breakthrough performance per watt, immersive camera and audio with enhanced AI-acceleration, lightning-fast 5G connectivity, and chip-to-cloud security in thin, fanless systems," says Miguel Nunes, vice president, product management, Qualcomm Technologies, Inc. "With Snapdragon 7c+ Gen 3, we are raising the bar in the entry-tier by extending 5G mobile computing across ecosystems. Whether for consumers, business, or education, Snapdragon compute platforms deliver the capabilities and experiences that our ecosystem customers and end users need."

AMD later this month is preparing to address investors as part of a yet-unknown event. The company typically hosts Financial Analyst Day events around Q1-Q2, and goes to the investors with substantial material on the current state of the organization, the products on offer, what's on the horizon, and how it could impact the company's financials. An alleged presentation related to the November 2021 event was leaked to the web. The presentation provides a guided tour of the entire product portfolio of the company, spanning server processors, compute accelerators, consumer graphics, some client processors, and the semi-custom business.

The presentation outlines that the company has so far successfully executed its roadmaps for the client-CPU, server-CPU, graphics, and compute-accelerator segments. In the client CPU segment, it shows a successful execution up to 2021 with the "Zen 3" microarchitecture. In the server space, it mentions successful execution for its EPYC processors up to "Zen 3" with its "Milan" processors, and confirms that its next-generation "Zen 4" microarchitecture, and its sister-architecture, the "Zen 4c," will be built on the 5 nm silicon fabrication node (likely TSMC N5). The presentation also details the recently announced "Milan-X" processor for existing SP3 platforms, which debuts the 3D Vertical Cache technology, bringing up to 96 MB of L3 cache per CCD, and up to 768 MB of L3 cache (804 MB L1+L2+L3 cache) per socket.Update 10:54 UTC: The presentation can now be found on the AMD Investor Relations website.

TSMC will commercialize its N3 (3 nm) EUV silicon fabrication node in 2022, with volume production set to commence in the second half of the year. The company is looking to maximize capacity on its current N5 (5 nm) node, which already serves major customers such as Apple. AMD is expected to utilize N5 allocation going into 2022 as its next-generation "Zen 4" processors are expected to leverage the node to drive up CPU core counts and caches. The company is also utilizing N6 (6 nm) for its CDNA2 compute accelerator logic dies. N5 could also power mobile application processors from several manufacturers.