Teledyne e2v has announced the DDR4T04G72M - the first radiation-tolerant DDR4 memory chip, featuring a total 4 GB capacity. Currently validated at 2133 MT/s, and targeting to offer 2400MT/s in the near future, this next-generation solution offers ultra-responsive low latency operation, while fitting into a highly compact form factor. Furthermore, high-reliability manufacturing and radiation-tolerant robustness makes it highly suitable for dealing with the rigors of space environments.

With 15 mm x 20 mm x 1.92 mm dimensions, this new space-grade device comprises an array of Micron based memory chips, integrated in a single package. It features a 72-bit bus, where 64 bits are dedicated to data and 8 bits to error correction code (ECC). Radiation tests have been performed on these memory chips and a single event effects (SEE) report is available from Teledyne e2v. In particular, the memory has been demonstrated to be single event latch-up (SEL) free up to 60+ MeV.cm²/mg.

Xilinx, Inc., the leader in adaptive and intelligent computing, today announced the industry's first 20-nanometer (nm) space-grade FPGA, delivering full radiation tolerance and ultra-high throughput and bandwidth performance for satellite and space applications. The new 20 nm Radiation Tolerant (RT) Kintex UltraScale XQRKU060 FPGA provides true unlimited on-orbit reconfiguration, over a 10x increase in digital signal processing (DSP) performance - ideal for payload applications - and full radiation tolerance across all orbits.

The XQRKU060 also brings high performance machine learning (ML) to space for the first time. A diverse portfolio of ML development tools supporting industry standard frameworks, including TensorFlow and PyTorch, enable neural network inference acceleration for real-time on-board processing in space with a complete "process and analyze" solution. The XQRKU060's dense, power-efficient compute with scalable precision and large on-chip memory, provides 5.7 tera operations per second (TOPs) of peak INT8 performance optimized for deep learning, a nearly 25X increase compared to the prior generation.

Today, Intel is pledging an additional $50 million in a pandemic response technology initiative to combat the coronavirus through accelerating access to technology at the point of patient care, speeding scientific research and ensuring access to online learning for students. Included in Intel's effort is an additional innovation fund for requests where access to Intel expertise and resources can have immediate impact. This is in addition to prior announcements of $10 million in donations that are supporting local communities during this critical time.

The world faces an enormous challenge in fighting COVID-19. Intel is committed to accelerating access to technology that can combat the current pandemic and enable new technology and scientific discovery that better prepares society for future crises. We hope that by sharing our expertise, resources and technology, we can help to accelerate work that saves lives and expands access to critical services around the world during this challenging time," said Bob Swan, Intel chief executive officer.

Xilinx, Inc. today announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry's highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.

Versal is the industry's first adaptive compute acceleration platform (ACAP), a revolutionary new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC's 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to-market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast and secure networks. The series doubles the compute density of currently deployed mainstream FPGAs and provides the adaptability to keep pace with increasingly diverse and evolving cloud and networking workloads.

Xperi Corporation today announced that it entered into a new patent and technology license agreement with SK hynix, one of the world's largest semiconductor manufacturers. The agreement includes access to Xperi's broad portfolio of semiconductor intellectual property (IP) and a technology transfer of Invensas DBI Ultra 3D interconnect technology focused on next-generation memory.

"We are delighted to announce the extension of our long-standing relationship with SK hynix, a world-renowned technology leader and manufacturer of memory solutions," said Craig Mitchell, President of Invensas, a wholly owned subsidiary of Xperi Corporation. "As the industry increasingly looks beyond conventional node scaling and turns toward hybrid bonding, Invensas stands as a pioneering leader that continues to deliver improved performance, power, and functionality, while also reducing the cost of semiconductors. We are proud to partner with SK hynix to further develop and commercialize our DBI Ultra technology and look forward to a wide range of memory solutions that leverage the benefits of this revolutionary technology platform."

CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced industry leading chipmaker Intel as its newest member. Intel is contributing the Advanced Interface Bus (AIB) to CHIPS Alliance to foster broad adoption.

CHIPS Alliance is hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics and Internet of Things (IoT) applications. The CHIPS Alliance project develops high-quality open source Register Transfer Level (RTL) code and software development tools relevant to the design of open source CPUs, SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon.

At Supercomputing 2019, Intel unveiled its vision for extending its leadership in the convergence of high-performance computing (HPC) and artificial intelligence (AI) with new additions to its data-centric silicon portfolio and an ambitious new software initiative that represents a paradigm shift from today's single-architecture, single-vendor programming models.

Addressing the increasing use of heterogeneous architectures in high-performance computing, Intel expanded on its existing technology portfolio to move, store and process data more effectively by announcing a new category of discrete general-purpose GPUs optimized for AI and HPC convergence. Intel also launched the oneAPI industry initiative to deliver a unified and simplified programming model for application development across heterogenous processing architectures, including CPUs, GPUs, FPGAs and other accelerators. The launch of oneAPI represents millions of Intel engineering hours in software development and marks a game-changing evolution from today's limiting, proprietary programming approaches to an open standards-based model for cross-architecture developer engagement and innovation.

Intel has today announced the Stratix 10 GX 10M - a Field Programmable Gate Array (FPGA) built on 14 nm technology that has an astonishing 43.3 Billion transistors, making it the largest FPGA in the world, dethroning the Xilinx with their previously largest Virtex VU19P FPGA which had a "mere" 35 Billion transistors. The Stratix 10 GX 10M is a home to over 10.2 million logic cells housed inside two large dies, connected by Intel's own Embedded Multi-die Interconnect Bridge (EMIB).

The 10M model is packing four additional dies besides the two for logic, also connected by EMIB, that feature 48 transceivers in total which have a combined bandwidth of up to 4.5Tb/s. If you are wondering about the bandwidth between all dies, then judging by EMIB's 25,920 connections, there is 6.5 Tb/s of inner-die bandwidth, meaning that components will not be starving for additional speeds to transfer the data. Additionally there are 2,304 user I/O pins, allowing for some creative integration solutions that involve plenty of ports for development purposes.

Intel today announced shipments of new Intel Stratix 10 DX field programmable gate arrays (FPGA). The new FPGAs are designed to support Intel Ultra Path Interconnect (Intel UPI), PCI-Express (PCIe) Gen4 x16 and a new controller for Intel Optane technology to provide flexible, high-performance acceleration. VMware is one of many early access program participants.

"Intel Stratix 10 DX FPGAs are the first FPGAs designed to combine key features that dramatically boost acceleration of workloads in the cloud and enterprise when used with Intel's portfolio of data center solutions. No other FPGA currently offers this combination of features for server designs based on future select Intel Xeon Scalable processors," said David Moore, Intel vice president and general manager, FPGA and Power Products, Network and Custom Logic Group.

Intel today announced that it has begun shipments of the first Intel Agilex field programmable gate arrays (FPGAs) to early access program customers. Participants in the early access program include Colorado Engineering Inc., Mantaro Networks, Microsoft and Silicom. These customers are using Agilex FPGAs to develop advanced solutions for networking, 5G and accelerated data analytics.

"The Intel Agilex FPGA product family leverages the breadth of Intel innovation and technology leadership, including architecture, packaging, process technology, developer tools and a fast path to power reduction with eASIC technology. These unmatched assets enable new levels of heterogeneous computing, system integration and processor connectivity and will be the first 10nm FPGA to provide cache-coherent and low latency connectivity to Intel Xeon processors with the upcoming Compute Express Link," said Dan McNamara, Intel senior vice president and general manager of the Networking and Custom Logic Group.

Xilinx, Inc., the leader in adaptive and intelligent computing, today announced the expansion of its 16 nanometer (nm) Virtex UltraScale+ family to now include the world's largest FPGA — the Virtex UltraScale+ VU19P. With 35 billion transistors, the VU19P provides the highest logic density and I/O count on a single device ever built, enabling emulation and prototyping of tomorrow's most advanced ASIC and SoC technologies, as well as test, measurement, compute, networking, aerospace and defense-related applications.

The VU19P sets a new standard in FPGAs, featuring 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. It enables the prototyping and emulation of today's most complex SoCs as well as the development of emerging, complex algorithms such as those used for artificial intelligence, machine learning, video processing and sensor fusion. The VU19P is 1.6X larger than its predecessor and what was previously the industry's largest FPGA — the 20 nm Virtex UltraScale 440 FPGA.

During Fortune's Brainstorm Tech conference in Aspen, Colorado, Intel's CEO Bob Swan took stage and talked about the company, about where Intel is now and where they are headed in the future and how the company plans to evolve. Particular focus was put on how Intel became "data centric" from "PC centric," and the struggles it encountered.

However, when asked about the demise of Moore's Law, Swan detailed the aggressiveness that they approached the challenge with. Instead of the regular two times improvement in transistor density every two years, Swan said that Intel has always targeted better and greater densities so that it would stay the leader in the business.

In recent conversations with Intel customers, two words kept coming up: disruption and opportunity. Disruption because almost every single executive I talk with has seen business disrupted in one way or another or is worried about keeping up with new technology trends and keeping a competitive edge. And opportunity because when these customers discuss their needs -- be it how to better leverage data, how to modernize their infrastructure for 5G or how to accelerate artificial intelligence (AI) and analytics workloads -- they realize the massive prospects in front of them.

To help our customers capitalize on the opportunities ahead, Intel has created a new organization that combines our network infrastructure organization with our programmable solutions organization under my leadership. This new organization is called the Network and Custom Logic Group.
Both original organizations executed on record design wins and revenues in 2018. Their merger allows Intel to bring maximum value to our customers by delivering unprecedented and seamless access to Intel's broad portfolio of products, from Intel Xeon processors SoC, FPGA, eASIC, full-custom ASIC, software, IP, and systems and solutions across the cloud, enterprise, network, embedded and IoT markets. To that end, FPGA and custom silicon will continue to be important horizontal technologies. And this is just the beginning of a continuum of Custom Logic Portfolio of FPGA, eASIC, and ASIC to support our customers' unique needs throughout their life cycles. No other company in the world can offer that.

Intel has announced that Sandra Rivera will take on a new role as the company's chief people officer and executive vice president, reporting to CEO Bob Swan. She will lead the human resources organization and serve as steward of Intel's culture evolution as it transforms to a data-centric company. Previously, Rivera was responsible for the Network Platforms Group, and served as Intel's 5G executive sponsor.

"Sandra is a role model for an Intel that is customer obsessed, collaborative and fearless while firmly grounded in trust, transparency and inclusivity. I am thrilled that Sandra will lead this critical part of our strategy to power a data-centric world," Swan said. "In a company driven by deep, technical talent, Sandra is an excellent technical leader who builds successful businesses by first building great teams. I am confident Sandra, as chief people officer, will help us accelerate our transformation and position our Intel team to play a bigger role in our customers' success."

Intel Corporation today reported first-quarter 2019 financial results. "Results for the first quarter were slightly higher than our January expectations. We shipped a strong mix of high performance products and continued spending discipline while ramping 10nm and managing a challenging NAND pricing environment. Looking ahead, we're taking a more cautious view of the year, although we expect market conditions to improve in the second half," said Bob Swan, Intel CEO. "Our team is focused on expanding our market opportunity, accelerating our innovation and improving execution while evolving our culture. We aim to capitalize on key technology inflections that set us up to play a larger role in our customers' success, while improving returns for our owners."

In the first quarter, the company generated approximately $5.0 billion in cash from operations, paid dividends of $1.4 billion and used $2.5 billion to repurchase 49 million shares of stock. In the first quarter, Intel achieved 4 percent growth in the PC-centric business while data-centric revenue declined 5 percent.

Intel announced today a brand-new product family, the Intel Agilex FPGA. This new family of field programmable gate arrays (FPGA) will provide customized solutions to address the unique data-centric business challenges across embedded, network and data center markets. "The race to solve data-centric problems requires agile and flexible solutions that can move, store and process data efficiently. Intel Agilex FPGAs deliver customized connectivity and acceleration while delivering much needed improvements in performance and power for diverse workloads," said Dan McNamara, Intel senior vice president, Programmable Solutions Group.

Customers need solutions that can aggregate and process increasing amounts of data traffic to enable transformative applications in emerging, data-driven industries like edge computing, networking and cloud. Whether it's through edge analytics for low-latency processing, virtualized network functions to improve performance, or data center acceleration for greater efficiency, Intel Agilex FPGAs are built to deliver customized solutions for applications from the edge to the cloud. Advances in artificial intelligence (AI) analytics at the edge, network and the cloud are compelling hardware systems to cope with evolving standards, support varying AI workloads, and integrate multiple functions. Intel Agilex FPGAs provide the flexibility and agility required to meet these challenges and deliver gains in performance and power.

Intel Tuesday unveiled a new portfolio of data-centric solutions consisting of 2nd-Generation Intel Xeon Scalable processors, Intel Optane DC memory and storage solutions, and software and platform technologies optimized to help its customers extract more value from their data. Intel's latest data center solutions target a wide range of use cases within cloud computing, network infrastructure and intelligent edge applications, and support high-growth workloads, including AI and 5G.

Building on more than 20 years of world-class data center platforms and deep customer collaboration, Intel's data center solutions target server, network, storage, internet of things (IoT) applications and workstations. The portfolio of products advances Intel's data-centric strategy to pursue a massive $300 billion data-driven market opportunity.

Today at Mobile World Congress (MWC) 2019, Intel announced the Intel FPGA Programmable Acceleration Card N3000 (Intel FPGA PAC N3000), designed for service providers to enable 5G next-generation core and virtualized radio access network solutions. The Intel FPGA PAC N3000 accelerates many virtualized workloads, ranging from 5G radio access networks to core network applications.

"As the mobile and telecommunications industry gears up for an explosion in internet protocol traffic and 5G rollouts, we designed the Intel FPGA PAC N3000 to provide the programmability and flexibility with the performance, power efficiency, density and system integration capabilities the market needs to fully support the capabilities of 5G networks," said Reynette Au, Intel vice president of marketing, Programmable Solutions Group.

Western Digital Corp. today announced at the RISC-V Summit three new open-source innovations designed to support Western Digital's internal RISC-V development efforts and those of the growing RISC-V ecosystem. In his keynote address, Western Digital's Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator.

These innovations are expected to accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments. Western Digital has taken an active role in helping to advance the RISC-V ecosystem, including multiple related strategic investments and partnerships, and demonstrated progress toward its stated goal of transitioning one billion of the company's processor cores to the RISC-V architecture.

Micron Technology, Inc., today announced that its GDDR6 memory, Micron's fastest and most powerful graphics memory, will be the high-performance memory of choice supporting Achronix's next-generation stand-alone FPGA products built on TSMC 7nm process technology. GDDR6 is optimized for a variety of demanding applications, including machine learning, that require multi-terabit memory bandwidth and will enable Achronix to offer FPGAs at less than half the cost of FPGAs with comparable memory solutions.

Achronix's high-performance FPGAs, combined with GDDR6 memory, are the industry's highest-bandwidth memory solution for accelerating machine learning workloads in data center and automotive applications.

This new joint solution addresses many of the inherent challenges in deep neural networks, including storing large data sets, weight parameters and activations in memory. The underlying hardware needs to store, process and rapidly move data between the processor and memory. In addition, it needs to be programmable to allow more efficient implementations for constantly changing machine learning algorithms. Achronix's next-generation FPGAs have been optimized to process machine learning workloads and currently are the only FPGAs that offer support for GDDR6 memory.

Intel today announced to press that they've scheduled an event for December 11th. The scheduled event should take the form of a small gathering of both Intel and press professionals, where Intel will be giving insights into its thought process and technologies with some in-depth presentations for technicians and engineers from the blue giant. Intel has become more and more secluded when it comes to the workings and architecture details of its technology advances, with the company even going so far as to cancel the (previously annual) Intel Developer Forums.

The event is apparently focusing on "architecture" considerations for future Intel products, so information shared could be strung with NDAs, and could fall under any product family Intel is working on (CPU, GPU, FPGA, AI...). We'll see what Intel has to share, and what kind of details (or watercolor ideas) can be painted on any future Intel products.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced several groundbreaking additions to its comprehensive semiconductor ecosystem that encompass next-generation technologies in foundry as well as NAND flash, SSD (solid state drive) and DRAM. Together, these developments mark a giant step forward for Samsung's semiconductor business.

"Samsung's technology leadership and product breadth are unparalleled," said JS Choi, President, Samsung Semiconductor, Inc. "Bringing 7 nm EUV into production is an incredible achievement. Also, the announcements of SmartSSD and 256GB 3DS RDIMM represent performance and capacity breakthroughs that will continue to push compute boundaries. Together, these additions to Samsung's comprehensive technology ecosystem will power the next generation of datacenters, high-performance computing (HPC), enterprise, artificial intelligence (AI) and emerging applications."

At today's Xilinx Developer Forum in San Jose, Calif., our CEO, Victor Peng was joined by the AMD CTO Mark Papermaster for a Guinness. But not the kind that comes in a pint - the kind that comes in a record book. The companies revealed the AMD and Xilinx have been jointly working to connect AMD EPYC CPUs and the new Xilinx Alveo line of acceleration cards for high-performance, real-time AI inference processing. To back it up, they revealed a world-record 30,000 images per-second inference throughput!

The impressive system, which will be featured in the Alveo ecosystem zone at XDF today, leverages two AMD EPYC 7551 server CPUs with its industry-leading PCIe connectivity, along with eight of the freshly-announced Xilinx Alveo U250 acceleration cards. The inference performance is powered by Xilinx ML Suite, which allows developers to optimize and deploy accelerated inference and supports numerous machine learning frameworks such as TensorFlow. The benchmark was performed on GoogLeNet, a widely used convolutional neural network.

Intel today extended its field programmable gate array (FPGA) acceleration platform portfolio with the addition of the new Intel Programmable Acceleration Card (PAC) with Intel Stratix 10 SX FPGA, Intel's most powerful FPGA. This high-bandwidth card leverages the Acceleration Stack for Intel Xeon CPU with FPGAs, providing data center developers a robust platform to deploy FPGA-based accelerated workloads. Hewlett Packard Enterprise* will be the first OEM to incorporate the Intel PAC with Stratix 10 SX FPGA along with the Intel Acceleration Stack for Intel Xeon Scalable processor with FPGAs into its server offering.

"We're seeing a growing market for FPGA-based accelerators, and with Intel's new FPGA solution, more developers - no matter their expertise - can adopt the tool and benefit from workload acceleration. We plan to use the Intel Stratix 10 PAC and acceleration stack in our offerings to enable customers to easily manage complex, emerging workloads," said Bill Mannel, vice president and general manager, HPC and AI Group, HPE.

It has been a rollercoaster Monday for AMD as it bled yet another bright executive. Jim Anderson, who led Computing and Graphics Group after the departure of Raja Koduri, and who is rumored to have conceived the idea of Threadripper and the client-segment monetization of the "Zen" architecture, left AMD to become CEO of Lattice Semiconductor, a company that designs FPGAs. Anderson will be paid an inducement award of company shares valued up to $2.9 million.

On the same day, AMD stock crossed $25 to close at $25.26 up 5.34 percent, a historic high since way back in 2006 as Intel was beginning to regain its footing with its Core processor family. This raises the company's market cap to $22.9 billion. AMD is better funded than ever (in over 12 years), to start a new GPU project, for example. CTO Mark Papermaster, in a company blog post assured customers that AMD is going all-in with 7 nanometer, and it could bank more heavily on TSMC to achieve its roadmap goals of first-to-market 7 nm CPU and GPU by end of the year.