SMART Modular Technologies, Inc. ("SMART"), a division of SGH and a global leader in memory solutions, solid-state drives, and hybrid storage announces its new Compute Express Link (CXL) Memory Module, the XMM CXL memory module. SMART's new DDR5 XMM CXL modules helps boost server and data center performance by enabling cache coherent memory to be added behind the CXL interface, further expanding big data processing capabilities beyond the current 8-channel/12-channel limitations of most servers.

The industry adoption of composable serial-attached memory architecture enables a whole new era for the memory module industry. Serial-attached memory adds capacity and bandwidth capabilities beyond main memory DIMM modules. Servers with XMM CXL modules can be dynamically configured for different applications and workloads without being shut down. Memory can be shared across nodes to meet throughput and latency requirements.

The industry has been undergoing significant changes in computing. Application specific hardware acceleration is becoming commonplace and new memory technologies are influencing the economics of computing. To address the need for an open architecture to allow full industry participation, the OpenCAPI Consortium (OCC) was founded in 2016. The architecture that was defined allowed any microprocessor to attach to coherent user-level accelerators, advanced memories, and was agnostic to the processor architecture. In 2021, OCC announced the Open Memory Interface (OMI). Based on OpenCAPI, OMI is a serial attached near memory interface that provides low latency and high bandwidth connections for main memory.

In 2019, the Compute Express Link (CXL) Consortium was launched to deliver an industry-supported cache-coherent interconnect for processors, memory expansion, and accelerators. In 2020, the CXL and Gen-Z Consortiums announced plans to implement interoperability between their respective technologies, and in early 2022, Gen-Z transferred its specifications and assets to the CXL Consortium.

High performance computing continues to evolve—meeting the ever-increasing demand for high efficiency, low-latency, rapid and seamless processing. The Gen-Z Consortium was founded in 2016 to create a next-generation fabric capable of bridging existing solutions while enabling new, unbounded innovation in an open, non-proprietary standards body.

In 2019, the CXL Consortium launched to deliver Compute Express Link (CXL ), an industry-supported cache-coherent interconnect designed for processors, memory expansion, and accelerators. The CXL Consortium and the Gen-Z Consortium established a joint memorandum of understanding (MOU) providing an opportunity for collaboration to define bridging between the protocols. This took the form of a joint working group that encouraged creativity and innovation between the two organizations toward the betterment of the industry as a whole.

The Compute Express Link (CXL) Consortium and Gen-Z Consortium today announced their execution of a Memorandum of Understanding (MOU), describing a mutual plan for collaboration between the two organizations. The agreement shows the commitment each organization is making to promote interoperability between the technologies, while leveraging and further developing complementary capabilities of each technology.

"CXL technology and Gen-Z are gearing up to make big strides across the device connectivity ecosystem. Each technology brings different yet complementary interconnect capabilities required for high-speed communications," said Jim Pappas, board chair, CXL Consortium. "We are looking forward to collaborating with the Gen-Z Consortium to enable great innovations for the Cloud and IT world."

The Gen-Z Consortium, an organization developing an open standard interconnect designed to provide high-speed, low latency, memory-semantic access to data and devices, today shared the Gen-Z Core Specification 1.0 is publicly available on its website. The Gen-Z Core Specification 1.0 enables silicon providers and IP developers to begin the development of products enabling Gen-Z technology solutions. Gen-Z's memory-centric standards-based approach focuses on providing an Open, reliable, flexible, secure, and high performance architecture for housing and analyzing the incredible amount of information at the edge coming into the data center.

"Our membership has grown significantly throughout 2017, now totaling more than fifty members, and we are proud of the hard work that has culminated with the release of our first Core Specification," said Gen-Z President, Kurtis Bowman. "We anticipate great things in 2018 as silicon developers begin implementing Gen-Z technology into their offerings and the ecosystem continues to grow."

While Intel has made some definite announcements and product launches of its own take on 3D XPoint technology with its Optane-based professional and consumer products, Micron has been a little late to the party on both. However, recent reports peg Micron's take on the new memory technology, under its QuantX brand, to ship later this year.

Micron is apparently taking a path that differs from Intel's though, in that it's looking to license its 3D Xpoint technology to other storage makers (not currently known which), in SSD or DDR-like formats, according to the company. However, these products will likely first target the enterprise space, with QuantX-based SSDs on the PCI-Express 3.0/NVMe protocols, with capacities of up to 1.4TB. Micron is aligning QuantX with emerging throughput technologies like Gen-Z, which could expand QuantX's reach towards the ARM server market, which has seen increasing interest in recent times.. The QuantX storage and memory will have their own dedicated controllers, sitting close to the CPU for quick data transfers, thus reducing potential bottlenecks.

AMD (NASDAQ: AMD) today unveiled its strategy to accelerate the machine intelligence era in server computing through a new suite of hardware
and open-source software offerings designed to dramatically increase performance, efficiency, and ease of implementation of deep learning workloads. New Radeon Instinct accelerators will offer organizations powerful GPU-based solutions for deep learning inference and training. Along with the new hardware offerings, AMD announced MIOpen, a free, open-source library for GPU accelerators intended to enable high-performance machine intelligence implementations, and new, optimized deep learning frameworks on AMD's ROCm software to build the foundation of the next evolution of machine intelligence workloads.

Inexpensive high-capacity storage, an abundance of sensor driven data, and the exponential growth of user-generated content are driving exabytes of data globally. Recent advances in machine intelligence algorithms mapped to high-performance GPUs are enabling orders of magnitude acceleration of the processing and understanding of that data, producing insights in near real time. Radeon Instinct is a blueprint for an open software ecosystem for machine intelligence, helping to speed inference insights and algorithm training.

A group of leading technology companies today announced the Gen-Z Consortium, an industry alliance working to create and commercialize a new scalable computing interconnect and protocol. This flexible, high-performance memory semantic fabric provides a peer-to-peer interconnect that easily accesses large volumes of data while lowering costs and avoiding today's bottlenecks. The alliance members include AMD, ARM, Cavium Inc., Cray, Dell EMC, Hewlett Packard Enterprise (HPE), Huawei, IBM, IDT, Lenovo, Mellanox Technologies, Micron, Microsemi, Red Hat, Samsung, Seagate, SK hynix, Western Digital Corporation, and Xilinx.

Modern computer systems have been built around the assumption that storage is slow, persistent and reliable, while data in memory is fast but volatile. As new storage class memory technologies emerge that drive the convergence of storage and memory attributes, the programmatic and architectural assumptions that have worked in the past are no longer optimal. The challenges associated with explosive data growth, real-time application demands, the emergence of low latency storage class memory, and demand for rack scale resource pools require a new approach to data access.