Intel's "Nova Lake-H" SoC, part of the Core Ultra 4000 Series, has reportedly surfaced. This is a second instance of "Nova Lake-H" surfacing, but this time without third-party annotations, and only coming with the raw, low-resolution SoC picture. This variant features a 4+8+4 configuration with 4 P-Cores, 8 E-Cores, and 4 LPE-Cores on a compute die made using Intel 18A-P technology. The package measures about 12x23 mm, resulting in a total die area of 276 mm², and includes both functional and dummy dies.

The first die is the graphics tile, built on the Intel 3-E node, embedding 4 Xe GPU cores and covering roughly 26 mm². Next to it is a dummy die occupying 21 mm², used for the structural integrity of the package. There is also a large 72 mm² die built on the Intel 18A-P node, hosting 4 LPE-Cores and serving as a central hub. Beside it is another 18A-P silicon die that functions as a peripheral control tile, measuring 58 mm². This configuration includes a compute tile, which hosts a 4P+8E-core configuration on the Intel 18A-P node, occupying 55 mm² of area.

Intel is moving some manufacturing capacity away from consumer chips to keep up with demand for its Xeon server processors. During its Q3 2026 earnings call, the company said it will convert some Intel 18A resources at its Oregon facilities to Intel 3, the node behind Xeon 6 "Granite Rapids." According to CFO Dave Zinsner, those 18A wafers "are generally going to build Panther Lake products." Zinsner also indicated that weaker PC demand gives Intel room to make the switch, as the company expects the PC slowdown to last at least through the first half of next year. CEO Lip-Bu Tan said the added Intel 3 capacity should be in production in the second half of 2027.

Intel CEO Lip-Bu TanThe industry continues to navigate one of the most significant supply shortages in the history, driven by the unprecedented demand for Super Intelligence. Against this backdrop, I am pleased by the progress we made growing our server supply in Q3. I'm mindful about the ongoing challenges we face in the future quarters to keep pace with the server demand.

Intel's upcoming "Nova Lake" lineup for mobile devices has been revealed in bare-die form, thanks to the Moore's Law Is Dead YouTube channel. Leading the lineup is the "Nova Lake-HX," featuring an 8+16+4 core configuration with 8 P-Cores, 16 E-Cores, and 4 LPE-Cores. The total silicon size measures 12x30 mm, amounting to 360 mm², which is divided across six different dies manufactured on various nodes. The first die is the graphics tile, built on the Intel 3-E node, embedding 4 Xe GPU cores and covering roughly 26 mm². Adjacent to it is a dummy die occupying 21 mm², used for the structural integrity of the package. Next, there is a large 72 mm² die built on the Intel 18A-P node, hosting 4 LPE-Cores and serving as a central hub. Beside it is another 18A-P silicon die that functions as a peripheral control tile, measuring 58 mm². Finally, Intel uses an external foundry for the main compute tile, which is on the TSMC N2P node and hosts the 8P+16E CPU core configuration. This compute tile occupies the largest area of 104 mm². Additionally, there is a passive tile next to it, with 85 mm² dedicated to the structural integrity of the package and the intended operation of the "Nova Lake-HX" chip.

Next, we move to the less powerful "Nova Lake-H" variant, which will feature a 4+8+4 configuration with 4 P-Cores, 8 E-Cores, and 4 LPE-Cores. This package is significantly smaller, measuring only 12x23 mm for a total die area of 276 mm², also consisting of both functional and dummy dies. The die configuration remains the same except for the main compute tile, which hosts a 4P+8E-core configuration on the TSMC N2P node, occupying 55 mm² of area. The adjacent passive die is also smaller, with an area of only 45 mm², while the peripheral control die, central hub die, and graphics tile are all made on Intel nodes and remain the same as in the "HX" variant.

SemiAnalysis has published a teardown of Intel's Panther Lake (Core Ultra 7 365), offering a rare look at 18A inside a shipping chip. Intel's 18A node brings advanced manufacturing technologies such as rear-side power delivery and a new transistor design, so its success is vital for the Foundry. The firm found the 18A compute logic to be similar in density to the TSMC N3E logic used in the 12-core Xe3 GPU tile. It also puts 18A about 18.6% denser than the Intel 3 GPU logic, using a representative-cell model. However, SemiAnalysis says 18A does not lead TSMC N3P, N2, or Samsung SF2 in peak density. It further cautions that whole-die density depends on cell mix and placement.

Panther Lake is Intel's first chip with RibbonFET gate-all-around transistors, and the first commercial implementation of PowerVia backside power delivery. SemiAnalysis counted four stacked ribbons per transistor, compared to three sheets on Samsung's SF2. Moreover, the Cougar Cove P-core takes roughly the same area as Lunar Lake's Lion Cove, even though L2 grew from 2.5 MiB to 3 MiB. Panther Lake's NPU 5 reportedly requires 36.9% less chip area than Lunar Lake's NPU 4, though the number of INT8 MAC units remains the same. SemiAnalysis describes the CPU cores as incremental updates.

Intel Foundry might win the contract to manufacture base dies for HBM4E memory from SK hynix, according to the South Korean Herald. Reportedly, SK hynix is considering diversifying its base die supplier from solely TSMC to a dual sourcing strategy involving both TSMC and Intel, with Intel Foundry potentially securing a significant portion of the contract. As readers may recall, HBM4E memory allows for the implementation of a base die with custom logic, with DRAM dies stacked on top. Until now, SK hynix has only considered TSMC for this application, but now Intel is also being considered.

For instance, customers could implement custom logic like memory controllers and PHYs directly on the HBM4E base die, significantly reducing the area occupied by these components on the main compute chiplet. SK hynix would send the design to Intel, which would then provide these base dies to SK hynix. The South Korean memory giant would subsequently stack DRAM on top. This approach would free up space on the main compute tile in any AI accelerator for more processing units, reduce latency, and significantly improve performance. However, the question remains as to which Intel node would be used. Up until HBM3E, SK hynix used its own nodes to manufacture base dies. However, as those are 10 nm class nodes, customers are now requiring something more advanced.

Intel, in a detailed presentation, detailed the package design of its next-generation Xeon 7 "Diamond Rapids" server processor. The processor is designed to be a versatile serial processing powerhouse for enterprise-scale agentic AI. Intel's design goal with the processor is to offer up to 256 P-cores, cushioned by up to 1.28 GB of last-level cache, per socket. The chip also features contemporary I/O, including PCI-Express Gen 6. Intel is leveraging its latest in-house foundry node, the Intel 18A-P, to design the core complex chiplets.

Xeon 7 "Diamond Rapids" is built on essentially the same disaggregation philosophy as AMD EPYC—that of CPU cores being spun out in small groups of CPU core complexes (CCXs) contained in CPU core dies (CCDs), groups of which interface with a centralized server I/O die (sIOD), which serves as a system agent and I/O hub. The "Diamond Rapids" MCM consists of two Fabric Hub Tiles (FHTs), four CPU core Base Tiles, and a total of 16 core chiplets, each containing 16 "Panther Cove" P-cores. The core-count per compute base tile is 64, and four of these add up to 256 cores.

Intel today announced a €5 billion ($5.7 billion) capital investment at its Leixlip campus in Ireland, marking the next phase in the site's capacity expansion. Global demand for AI and high-performance computing is driving the need for advanced silicon to power AI Factories, and Intel is scaling capacity in Ireland to deliver Intel Xeon 6 and next gen Intel Xeon built on its Intel 3 node. This strategic investment expands current production output, advances research and development activities and utilises capacity across existing cleanroom space, strengthening Europe's semiconductor supply chain and serving industry need.

The expansion involves upgrading existing fabrication facilities and the installation of leading-edge manufacturing equipment. Key infrastructure enhancements include the expansion of the automated track system to integrate disparate campus modules into a singular, high-velocity production environment.

Intel's 18A node is officially space-grade, according to documentation on Intel's website. A document that initially went unnoticed has been published, detailing a new "Starfire" generation of processors built on the 18A node and designed for space operations. Intel has designated two SKUs for orbital computing, each equipped with four P-Cores and four LPE-Cores, resulting in an eight-core SoC design. One is optimized for low-power operations with clocks adjusted for efficiency, while the other is designed for performance. The Low Power edition tunes its four P-Cores to 1.0 GHz, while the four LPE-Cores run at 850 MHz. For the Performance version, Intel has increased the frequency of P-Cores to 3.1 GHz, with LPE-Cores reaching up to 2.1 GHz.

Both SKUs feature a GPU tile built on the Intel 3 node, which includes 4 Xe cores with 64 EUs. On the Low Power SKU, these Xe cores operate between 800 MHz and 1.0 GHz, while the Performance SKU boosts this to 2.0 GHz. The total package for the Low Power version remains at 10 W TDP, while the Performance SKU is capped at 35 W TDP. Additionally, Intel includes an NPU on both versions, with a compute capability of 45 TOPS on the Low Power version and up to 75 TOPS on the Performance SKU using INT8 precision. Beyond specifications, "Starfire" can operate within a T-Junction range from -55°C to 125°C. This range, alongside TID, SEL, and SEE radiation hardening certifications, introduces the first 18A silicon to space, ideal for orbital computation. Intel targets this quarter, Q3, for samples.

At the VLSI Symposium held in Hawaii, Intel unveiled the new Intel 18A-P foundry node, a significant refinement of the Intel 18A node that carves out room for a 9% increase in performance at iso-power. The company announced that it commenced risk-production on this new node, and has earmarked it for its next-generation Xeon "Diamond Rapids" server processor. Besides 9% increase in performance at iso-power, Intel 18A-P is claimed to offer an 18% power reduction at iso-performance, a 20-40% improvement in die-level thermal resistance, and a 10-30% improvement in Via resistance in performance-critical layers.

The company detailed the physical changes to the Intel 18A node made to achieve these gains. Intel added new cell options across its 180HP and 160HD libraries to support a wider range of products. For low-power designs, it introduced W1 and W1.5 cells. For high-performance needs, it added the W3P cell, which utilizes a "dual contact" design to boost performance without exceeding the footprint of the existing W3 cell. The company significantly lowered thermal resistance by integrating a new heat-conducting material on the front side of the die. Intel also updated its EDA tools to support thermally-aware layouts, allowing designers to better manage heat dissipation at the structural level.

We have been reporting on the intense demand in the CPU sector currently sweeping the industry. AMD and Intel have sold out their inventories, and lead times are now weeks long. However, Intel, which manufactures a large part of its CPU portfolio, has been handling the situation differently. According to Intel and confirmed by industry analyst Ben Bajarin, the company is repurposing some of the dies found on the very edge of the silicon wafer, which would have otherwise become silicon scrap, into products that customers are eager to buy. This approach allows even some SKUs, which may have been flawed due to various effects like silicon node yield, to find new life through repurposing. Intel's customers are so eager for CPUs that higher-end parts, which would typically be discarded, are now being sold as independent SKUs. No silicon is left behind.

For example, when Intel produces a Xeon 6 "Granite Rapids" CPU on the Intel 3 node, the CPU compute die can accommodate up to 44 cores per die, but some are disabled for yield and power reasons. When the yield fails, these compute dies are repurposed into SKUs with lower core counts, as it costs Intel money to manufacture the die, and wasting it would be a significant loss of resources. However, when the die doesn't achieve satisfactory yield on the Intel 3 production line, the company would usually discard it if it can't extract a reasonable number of working cores. Amidst one of the highest-ever recorded CPU shortages, Intel is doing the opposite. The company is using these defective or scrap dies and packaging them into lower-class SKUs to sell to its customers, as any CPU availability is crucial, and customers are eagerly purchasing them. Imagine a wafer edge, which is round, having only a few working P-Cores, and that being packaged into a CPU that a hyperscaler would integrate into their offering.

Intel posted strong Q1 2026 earnings results, indicating improvements across multiple verticals, from Intel Products to Intel Foundry divisions. Both groups experienced operational enhancements, but Intel Foundry achieved a significant milestone: yield improvement across all major foundry nodes currently in high-volume manufacturing. This includes Intel 4, Intel 3, and 18A nodes, which power the majority of Intel's product portfolio. In the latest Q1 2026 earnings call, Intel CFO David Zinsner noted that the company continues to improve yields on its older nodes, such as Intel 4 and Intel 3, while refining the yield of the current top-performing 18A node to reduce waste and increase the number of functional chips, even in larger dies.

David Zinsner, Intel CFOIntel Foundry operating loss in Q1 was $2.4 billion, improved $72 million quarter-over-quarter as better yields across Intel 4, Intel 3, and 18A drove higher gross margins. This was mostly offset by increased operating expenses associated with an intentional step-up in Intel 14A investments to support both internal and external customer evaluations. As a reminder, Intel Foundry carries the bulk of the cost associated with the early ramp of Intel 18A, and we expect Intel Foundry's operating loss to improve through the year as 18A continues to ramp into volume and yields improve further. Within the quarter, Intel Foundry delivered output above our expectations, drove steady improvements in yields, and met key 14A milestones.

Intel's recently announced Core Ultra Series 3 "Panther Lake-H" mobile processor die-shot has been annotated by Kurnal Insights. "Panther Lake-H" is a disaggregated processor, just like its predecessor, "Arrow Lake-H," and "Meteor Lake," but Intel has followed a disaggregation plan resembling that of "Lunar Lake," where an SoC tile contains the CPU cores across both the main compute complex and low-power island; the NPU, and the processor's main integrated memory controllers; the Graphics tile contains the iGPU's number-crunching machinery, the Xe cores; while the I/O tile contains the chip's various platform I/O components.

The SoC tile is built on the Intel 18A foundry node. On the mainstream notebook "Panther Lake-H" processor variants, such as the one annotated below, the Graphics tile contains 4 Xe cores, and is built on the Intel 3 foundry node. On the ultraportable "Panther Lake-U" processor with powerful integrated graphics meant for devices lacking discrete GPUs, the Graphics tile has 12 Xe cores, and is built on the TSMC N3E node. The I/O tile continues to be built on the same TSMC N6 node as the ones on previous-generation "Arrow Lake" processors.

Intel used its MWC conference in Barcelona to showcase its most core-dense Xeon 6+ processor, codenamed "Clearwater Forest." As one of Intel's most complex chiplet designs, the package combines 12 compute chiplets manufactured on an Intel 18A node with three active base tiles on Intel 3 and two I/O tiles on Intel 7. In this configuration, each compute tile contains six modules of four "Darkmont" efficiency cores, providing 24 E-cores per tile and a maximum of 288 "Darkmont" E-cores on a single socket. A two-socket system, therefore, approaches 576 cores. The design connects clusters with a high-bandwidth on-chip fabric and stacks die using Foveros Direct 3D, while EMIB links connect multiple tiles in a 2.5D arrangement.

Each "Darkmont" E-core comes with a 64 KB instruction cache, a wider front end, and a larger out-of-order window to sustain more in-flight work. Execution resources and the number of execution ports have been increased to improve parallel integer and vector throughput. Physically, clusters are grouped in four-core units sharing about 4 MB of L2 cache per group, and the package-level last-level cache can exceed a gigabyte, with about 1,152 MB of combined last-level cache across the package. "Clearwater Forest" supports the existing Xeon server platform socket, 12 memory channels, and broad I/O, including 96 PCIe 5.0 lanes and 64 CXL 2.0 lanes. Memory speed targets push toward DDR5-8000.

Yesterday, after the equity market closed, Intel announced its Q4 and full-year 2025 earnings, along with weaker-than-expected guidance for Q1 2026. As a result, Intel's stock is anticipated to open 11% lower today. During the Q4 earnings call, Intel's CFO, David Zinsner, explained the reasons behind the reduced outlook, despite the increasing demand for Intel products. The situation arose due to hyperscalers demanding more units. Intel's discussions with these customers indicated a preference for high core count solutions rather than increased unit shipments. Consequently, Intel adjusted its inventory and internal wafer supply to maintain reasonable stock levels while consistently shipping new units. However, hyperscalers have since been ordering larger quantities, leading to a temporary shortage of Xeon processors for the Data Center and AI (DCAI) group. To address this, Intel plans to redirect some resources from the Client Computing Group (CCG) to support Xeon CPU production.

Intel CFO David ZinsnerBoth (DCAI and CCG) will be down as a function of supply. Obviously, we're shifting as much as we can over to data center to meet the high demand, but we can't completely vacate the client market. So we're trying to support both as best we can and obviously work our way out of this supply issue. I do believe that the first quarter is the trough. We will improve supply in the second quarter. Part of the challenge is that in the third and fourth quarter of 2025, we lived off of supply, but we also had a reasonable chunk of finished goods inventory to also work through. Unfortunately, that is now down to kind of 40% of what it was at peak levels.

Intel was presenting at 2025 UBS Global Technology and AI Conference, revealing interesting details about the demand for its "Lunar Lake" and "Arrow Lake" processors. On the question from one of the analysts that some assume Intel isn't selling its new products and there is no demand, Intel's John Pitzer answered "Quite frankly, if we had more Granite wafers, we'd be selling more Granite. If we had more Lunar Lake wafers, we'd be selling more Lunar Lake. If we had more Arrow Lake wafers, we'd be selling more Arrow Lake. And so I think we feel pretty good about where we are in the AI PC transition. And we feel very good about where we are in the initial phase of the Granite ramp, which is our latest generation server part."

This puts an end to the speculation that Intel's products aren't selling well, and the recent Q3 revenue figure of $13.7 billion matches that. Additionally, Intel made comments about its internal and external manufacturing capacity. Intel's "Lunar Lake" and "Arrow Lake" are SoCs that are fully outsourced to TSMC, with Intel performing the packaging. Hence, Intel's limited capacity booked at TSMC is not enough to satisfy the demand. However, starting with "Panther Lake," the wafer supply is getting back in-house as 18A yields mature. All the "Panther Lake" logic dies will be manufactured in-house, compared to 0% of logic dies manufactured in-house for "Arrow Lake" and "Lunar Lake."

Intel recently added another "Panther Lake" engineering sample to public benchmarking records. Geekbench reported a Core Ultra 7 366H processor featuring a four-core Xe3 integrated GPU built on the Intel 3 node. The system achieved a Vulkan API score of 22,813, placing this compact Xe3 configuration within the entry-level discrete GPU category. This score is roughly 26% higher than the 4-core AMD Radeon 840M and slightly surpasses the mobile GTX 1050 Ti, though it remains below the 8-core Radeon 860M. This indicates that Intel is now reaching performance levels similar to AMD's "Krackan Point" APUs with RDNA 3.5, making it suitable for gaming on the go.

The processor details in the listing match previous leaks. The Core Ultra 7 366H has a 16-core design, which includes 4 performance cores, 8 efficient cores, and 4 low-power efficient cores. It operates at a base clock speed of 2.00 GHz and can boost up to 4.8 GHz. The processor also includes approximately 18 MB of L3 cache. The Xe3 GPU increases its L2 cache to 4 MB in the 4-core configuration and 16 MB in the 12-core configuration, equating to 1 MB per core on the smaller tile and 1.5 MB per core on the larger tile. Additionally, Xe3 features updated ray tracing units with faster bounding-box traversal and a larger BVH cache, enhancing performance consistency in hybrid-rendered games. Nonetheless, this is an interesting preview of the upcoming "Panther Lake" Xe3 iGPU, and we expect to see more at CES 2026.

AEWIN is excited to unveil the BIS-5231 Series, a high-performance 2U general purpose server built on Intel's latest Xeon 6 processors manufactured with Intel 3 process technology. Powered by dual Intel Xeon 6700/6500-series processors with P-cores or E-cores, the BIS-5231 delivers exceptional compute density and scalability. It offers up to eight PCIe Gen 5 expansion slots and twelve storage drive bays with SAS/SATA or NVMe options to meet diverse deployment requirements.

The BIS-5231 Series is equipped with 16 DDR5 RDIMM slots supporting speeds up to 6400 MT/s, two M.2 PCIe Gen 5 slots, two USB 3.1 ports, four RJ45 10GbE ports, and one RJ45 GbE IPMI port without requiring additional PCH needed. The BIS-5231A model provides twelve 3.5-inch LFF drive bays and eight PCIe Gen 5 slots plus an OCP 3.0 slot while the BIS-5231B offers twelve U.2 NVMe drive bays and seven PCIe Gen 5 slots plus an OCP 3.0 slot. The expansion slots are suitable for high-throughput NICs and GPU cards for data-intensive and AI-driven workloads.

Intel is gearing up for a return to the high-end desktop (HEDT) workstation market with the launch of the "Granite Rapids-WS" Xeon processors. A well-known hardware leaker, @momomo_us, has provided a list of potential SKUs, detailing their L3 cache capacities and clock speeds. At the top of this preliminary list is a SKU labeled as the "698X," featuring 336 MB of L3 cache and a clock speed of 2.0 GHz across all cores. The lower clock speed combined with naming conventions suggesting it's a top end SKU tier suggests this should be a higher-core SKU, though this is yet to be confirmed. The Granite Rapids-WS design is based on Intel's XCC server compute dies, incorporating two compute tiles that deliver up to 86 cores with two I/O tiles for connectivity, such as PCIe and memory controllers. To exceed 86 cores, Intel would likely need to adopt the larger UCC die and a bigger package.

The specifics of memory support for the workstation SKU are still uncertain. However, the server XCC family supports DDR5-6400 and can achieve higher effective speeds with MR-DIMMs. For workstations, Intel is likely to opt for an eight-channel memory configuration to balance capacity and board complexity, although a 12-channel memory setup is also possible. The Granite Rapids-WS processors are derived from Intel's server XCC dies, allowing for a quicker path to higher core counts in workstations. These "Granite Rapids" server dies are modified with a new socket and package to suit the specific needs of workstations. Intel manufactures the I/O die for Granite Rapids on the Intel 7 node, while the compute tiles are produced using Intel 3.

Intel's Q3 earnings delivered a solid number, but a few interesting things are happening at Intel's Fabs that aren't related to any leading-edge node production. According to Intel CFO David Zinsner, "In Q3, Intel Foundry delivered Intel 10 and 7 volume above expectations," indicating that demand for Intel's products built on these nodes is significantly exceeding supply. Zinsner noted, "Capacity constraints, especially on Intel 10 and Intel 7, limited our ability to fully meet demand in Q3 for both data center and client products," suggesting strong demand for Core and Xeon processors built on these nodes.

Intel first introduced Intel 7 node, previously known as 10 nm Enhanced SuperFin, with 12th Generation "Alder Lake." However, that is now discontinued and Intel continues to ship 13th Generation "Raptor Lake" and 14th Generation Core "Raptor Lake Refresh" client CPUs on the Intel 7 node. For Xeon server chips, the company uses the Intel 7 node for the 4th Generation "Sapphire Rapids," 5th Generation "Emerald Rapids" Xeon Scalable and manufactures the I/O die for the latest "Granite Rapids" Xeon 6, where the compute dies are made on the Intel 3 node. High demand from the gaming sector for 13th and 14th Gen gaming CPUs, along with strong demand for Xeon processors, has created a manufacturing bottleneck. Intel will prioritize delivering data center products first and gaming products second.

Intel announced this week that its Panther Lake processors have entered volume production at Fab 52 using the company's 18A node, which is touted as the first 2 nm-class process to achieve high-volume manufacturing. This milestone gives Intel a slight timing advantage over rival foundries like TSMC, with its N2 node, and Samsung with its SF2 node. However, being first does not guarantee a lasting lead. Customers, partners, and investors will focus on Intel's ability to maintain parametric yields, control manufacturing costs per unit, and expand 18A beyond limited compute tiles. While Intel has shared improvements in defect density and early functional test results, comprehensive parametric yield metrics that demonstrate consistent achievement of power, performance, and frequency targets remain undisclosed. Initial shipments and early ramp figures will determine whether this production start is symbolic or substantive for Intel's manufacturing revival.

At the transistor level, 18A node introduces two major innovations: RibbonFET gate-all-around transistors and PowerVia backside power delivery. RibbonFET replaces vertical FinFET fins with thin horizontal silicon ribbons wrapped by gate material, enhancing electrostatic control, reducing leakage, and allowing shorter gate lengths. Intel reports approximately 5-10% shorter gate lengths when transitioning from FinFET to RibbonFET on 18A and claims over 20% reduction in per-transistor power. PowerVia relocates the power network to the wafer's backside, freeing up front-side metal for signal routing, shortening power paths, and reducing voltage drop at high switching rates. Together, these changes lower switching energy and provide designers with more flexibility to increase frequencies or reduce power consumption in notebooks and other mobile designs.

Today Intel revealed the architectural details for the company's next generation client processor Intel Core Ultra series 3 (code-named Panther Lake) which is expected to begin shipping later this year. Panther Lake is the company's first product built on Intel 18A, the most advanced semiconductor process ever developed and manufactured in the United States.

Intel also previewed Xeon 6+ (code-named Clearwater Forest), its first Intel 18A-based server processor, which is expected to launch in the first half of 2026. Both Panther Lake and Clearwater Forest, as well as multiple generations of products built on Intel 18A, are being manufactured at Fab 52, Intel's new, state-of-the-art factory in Chandler, Arizona - a key milestone as Intel invests in strengthening American technology and manufacturing leadership and building a resilient semiconductor supply chain.

[Editor's note: Our in-depth tech preview article of Panther Lake is now live]

Intel used Hot Chips to pull back the curtain on "Clearwater Forest", its next-generation E-core Xeon. The company has paired major architectural upgrades with its newest 18A process and advanced 3D Foveros packaging paired with EMIB. The chip replaces "Sierra Forest" and is built around the new "Darkmont" efficiency cores. Intel says Clearwater Forest will ship in a massive chiplet package using the 18A node for the compute pieces while relying on Foveros Direct 3D for stacking. The company is pitching this design as a showcase of what its foundry and packaging teams can now deliver.

Under the hood, the Darkmont E-core leans heavily on a wider, more parallel front end and a beefed-up out-of-order engine. Intel disclosed a 64 KB instruction cache per core and an expanded decoder that can handle more instructions per cycle than the previous "Crestmont" E-core design. Reorder and allocation structures have evolved, allocation units have been increased, and the out-of-order window has been enlarged to accommodate more in-flight work. Execution resources were also multiplied, with many more execution ports for integer and vector math, allowing the cores to sustain much higher parallel throughput.

Intel's presentation at the VLSI Symposium in Japan offered a detailed look at the upcoming Intel 18A process, which is set to enter mass production in the second half of 2025. This node combines Gate-All-Around transistors with the PowerVia backside power delivery network, resulting in a completely new metal stack architecture. By routing power through the rear of the die, Intel has been able to tighten interconnect pitches on critical layers while relaxing spacing on the top layer, improving yield and simplifying fabrication. In standardized power, performance, and area tests on an Arm core sub-block, Intel 18A demonstrated roughly 15% higher performance at the same power draw compared to Intel 3. When operating at 1.1 volts, clock speeds increase by up to 25% without incurring additional energy costs, and at around 0.75 volts, performance can rise by 18%, or power consumption can drop by nearly 40%.

Under the hood, the process features significant cell height reductions: performance-tuned cells measure 180 nanometers tall, while high-density designs sit at 160 nanometers, both smaller than their predecessors. The front-side metal layers have been reduced from between 12 and 19 on Intel 3 to between 11 and 16 on Intel 18A, with three additional rear metal layers added for PowerVia support. Pitches on layers M1 through M10 have been tightened from as much as 60 nanometers down to 32 nanometers before easing again in the upper layers. Low-NA EUV exposure is used on layers M0 through M4, cutting the number of masks required by 44% and simplifying the manufacturing flow. Intel plans to debut 18A in its low-power "Panther Lake" compute chiplet and the efficiency-core-only Clearwater Forest Xeon 7 family. A cost-optimized 17-layer variant, a balanced 21-layer option, and a performance-focused 22-layer configuration will address different market segments.

Intel has updated its 18A node website with the message, "Intel 18A is now ready for customer projects with the tape outs beginning in the first half of 2025: contact us for more information." The contact hyperlink includes an email where future customers can direct their questions to Intel. Designed as a turnaround node for Intel, 18A carries industry-leading features like SRAM density scaling comparable with TSMC's N2, 15% better performance per watt, and 30% better chip density vs. the Intel 3 process node used in Intel Xeon 6, as well as PowerVia backside-power delivery to increase transistor density.

Other features like RibbonFET are the first to replace FinFET transistors, making gate leakage a tighter control. Interestingly, Intel's first products to use the 18A node are client CPUs "Panther Lake" and "Clearwater Forest" Xeon CPUs for data centers. External Intel Foundry customers using the 18A node include Amazon's AWS, Microsoft for its internal silicon for Azure, and Broadcom exploring 18A-based designs. The process of gaining customers for advanced manufacturing is complex, as many existing Samsung/TSMC customers are not risking their capacity and contracts with established advanced silicon makers. However, if Intel's first few customers prove successful, many others could flock over to Intel's fabs as geopolitical tensions are questioning whether the current models of the semiconductor supply chain are feasible in the future. If US companies and startups decide to move with Intel for their chip manufacturing, Intel could experience a complete recovery.

Intel has unveiled some interesting advances in semiconductor manufacturing at the International Solid-State Circuits Conference (ISSCC), showcasing the capabilities of its highly anticipated Intel 18A process technology. The presentation highlighted significant improvements in SRAM bit cell density. The PowerVia system, coupled with RibbonFET (GAA) transistors, is at the heart of Intel's node. The company demonstrated solid progress with their high-performance SRAM cells, achieving a reduction from 0.03 µm² in Intel 3 to 0.023 µm² in Intel 18A. High-density cells showed similar improvement, shrinking to 0.021 µm². These advancements represent scaling factors of 0.77 and 0.88 respectively, which are significant achievements in SRAM technology, once thought to be done with scaling benefits.

Implementing PowerVia technology is an Intel-first approach to addressing voltage drops and interference in processor logic areas. Using an "around the array" scheme, Intel strategically applies PowerVias to I/O, control, and decoder elements while optimizing bit cell design without a frontal power supply. The macro bit density of 38.1 MBit/mm² achieved by Intel 18A puts the company in a strong competitive position. While TSMC reported matching figures with their N2 process, Intel's comprehensive approach with 18A, combining PowerVia and GAA transistors, could challenge Smausng and TSMC, with long-term aspirations to compete for premium clients currently served by TSMC, including giants like NVIDIA, Apple, and AMD.