On February 26, 2024, AMD received new research related to an industry-wide DRAM issue documented in "ZENHAMMER: Rowhammering Attacks on AMD Zen-based Platforms" from researchers at ETH Zurich. The research demonstrates performing Rowhammer attacks on DDR4 and DDR5 memory using AMD "Zen" platforms. Given the history around Rowhammer, the researchers do not consider these rowhammering attacks to be a new issue.

Mitigation
AMD continues to assess the researchers' claim of demonstrating Rowhammer bit flips on a DDR5 device for the first time. AMD will provide an update upon completion of its assessment.

Researchers at Graz University of Technology and the Helmholtz Center for Information Security have released their paper on CacheWarp—the latest vulnerability affecting some of the prior generation AMD EPYC CPUs. Titled CVE-2023-20592, the exploit targets first-generation EPYC Naples, second-generation EPYC Rome, and third-generation EPYC Milan. CacheWarp operates by exploiting a vulnerability in AMD's Secure Encrypted Virtualization (SEV) technology, specifically targeting the SEV-ES (Encrypted State) and SEV-SNP (Secure Nested Paging) versions. The attack is a software-based fault injection technique that manipulates the cache memory of a virtual machine (VM) running under SEV. It cleverly forces modified cache lines of the guest VM to revert to their previous state. This action circumvents the integrity checks that SEV-SNP is designed to enforce, allowing the attacker to inject faults without being detected.

Unlike attacks that rely on specific guest VM vulnerabilities, CacheWarp is more versatile and dangerous because it does not depend on the characteristics of the targeted VM. It exploits the underlying architectural weaknesses of AMD SEV, making it a broad threat to systems relying on this technology for security. The CacheWarp attack can bypass robust security measures like encrypted virtualization, posing a significant risk to data confidentiality and integrity in secure computing environments. AMD has issued an update for EPYC Milan with a hot-loadable microcode patch and updated the firmware image without any expected performance degradation. And for the remaining generations, AMD states that no mitigation is available for the first or second generations of EPYC processor (Naples and Rome) since the SEV and SEV-ES features are not designed to protect guest VM memory integrity, and the SEV-SNP is not available.

A huge thank you to all of our Age of Empires II: Definitive Edition players for your record-setting support and to everyone who has played Return of Rome so far! This is the biggest DLC launch in Age of Empires II history! We've been listening to your feedback and would like to share our plan to address the concerns regarding your in-game experience and your desire to see Age of Empires campaigns in Return of Rome.

We are actively monitoring the issues you're reporting and will address them as soon as possible. This includes disruptions to your hotkey settings, issues preventing UI mods from loading in correctly, and games failing to load. The hotkey disruption was a one-time adjustment. You can visit our support page if you need help getting them reconfigured. Our teams are paying close attention to the reports you make and are thankful for your continued trust.

Over the last 20 years, Age of Empires II has consistently been viewed as the cornerstone of this great RTS franchise. Praised for its myriad mechanical improvements over the first game, unique units and the addition of gates to stop yourself accidentally imprisoning your on-screen warriors, Age of Empires II ushered in an era almost as unforgettable as the in-game factions we love to roleplay.

But a groundbreaking sequel always has an origin story that started it all, and the first Age of Empires title is by no means being left behind. The latest expansion, Return of Rome, is set to bring integral parts of the game's original content into Age of Empires II: Definitive Edition as its own self-contained offering, plus some brand new additions for fans to get stuck into.

Everything you need to know - what to expect with the newest Return of Rome DLC for Age of Empires II: Definitive Edition. What is Return of Rome? Return of Rome is a completely new type of expansion, which brings classic Age of Empires gameplay, style and key experiences as a brand new self-contained experience. Also...

Starting this weekend, some of your favorite content creators are ready to show YOU an exclusive preview of the upcoming DLC for Age of Empires II: Definitive Edition - Return of Rome. Want to know more about the upcoming addition of the 16 Age of Empires civilizations, the brand-new Lac-Viet, or the new Romans to Age of Empires II: Definitive Edition? Well, we have fantastic news for you: some of your favorite content creators have been granted early access to the Return of Rome DLC, and you'll be getting a sneak preview of the exclusive units, civilization bonuses, and other new additions ahead of release!

Where were you in 1998? Perhaps listening to Cher's Believe, watching Titanic, playing with your Tamagotchi and relaxing on your inflatable couch? Or were you playing the Age of Empires DLC The Rise of Rome? This beloved evolution of the first Age of Empires game has taken on a new form and joined the Definitive Edition era in the Return of Rome DLC for Age of Empires II: Definitive Edition.

Yes, you read that correctly, Age of Empires content available in Age of Empires II: Definitive Edition. Bringing the civilizations and action of ancient worlds to AoE II: DE. Purchasers will be able to switch to Return of Rome in the game's main screen and take on fresh challenges.

The Return of Rome campaign is set for a May 16 2023 release date according to a tweet posted by the official Age of Empires account. The latest campaign expansion for Age of Empires II: Definitive Edition follows several (almost) yearly DLC drops since the re-mastered strategy game's debut in late 2019 - Lords of the West (January 2021), Dawn of the Dukes (August 2021) and Dynasties of India (April 2022). Last year's India campaign added a significant amount of content, in the form of three new civilizations: the Bengalis, Dravidians, and Gurjaras. Three new campaigns were added to the base game and introduced a trio of new empires: Babur, Rajendra, and Devapala. The entire Indian civilization within the game was renamed to the Hindustanis.

Age of Empires II: Definitive Edition - Return of Rome was first announced, albeit briefly, during a livestream on 25 October 2022, which celebrated the 25th anniversary of the real time strategy game series. Details are scarce about the actual content on offer, but the upcoming campaign is expected to feature all 16 of the original civilizations from the first entry in the franchise (AoE) according to an internal Xbox Games Studios memo.

AMD EPYC class of enterprise processors has gotten infected by as many as 22 different security vulnerabilities. These vulnerabilities range anywhere from medium to high severity, affecting all three generations of AMD EPYC processors. This includes AMD Naples, Rome, and Milan generations, where almost all three are concerned with the whole 22 exploits. There are a few exceptions, and you can find that on AMD's website. However, not all seems to be bad. AMD says that "During security reviews in collaboration with Google, Microsoft, and Oracle, potential vulnerabilities in the AMD Platform Security Processor (PSP), AMD System Management Unit (SMU), AMD Secure Encrypted Virtualization (SEV) and other platform components were discovered and have been mitigated in AMD EPYC AGESA PI packages."

AMD has already shipped new mitigations in the form of AGESA updates, and users should not fear if they keep their firmware up to date. If you or your organization is running on AMD EPYC processors, you should update the firmware to avoid any exploits from happening. The latest updates in question are NaplesPI-SP3_1.0.0.G, RomePI-SP3_1.0.0.C, and MilanPI-SP3_1.0.0.4 AGESA versions, which fix all of 22 security holes.

AMD is expected to announce its upcoming EPYC lineup of processors for server applications based on the new Zen 3 architecture. Codenamed "Milan", AMD is continuing the use of Italian cities as codenames for its processors. Being based on the new Zen 3 core, Milan is expected to bring big improvements over the existing EPYC "Rome" design. Bringing a refined 7 nm+ process, the new EPYC Milan CPUs are going to feature better frequencies, which are getting paired with high core counts. If you are wondering how Zen 3 would look like in server configuration, look no further because we have the upcoming AMD EPYC 7543 32-core processor benchmarked in Geekbench 4 benchmark.

The new EPYC 7543 CPU is a 32 core, 64 thread design with a base clock of 2.8 GHz, and a boost frequency of 3.7 GHz. The caches on this CPU are big, and there is a total of 2048 KB (32 times 32 KB for instruction cache and 32 times 32 KB for data cache) of L1 cache, 16 MB of L2 cache, and as much as 256 MB of L3. In the GB4 test, a single-core test produced 6065 points, while the multi-core run resulted in 111379 points. If you are wondering how that fairs against something like top-end Intel Xeon Platinum 8280 Cascade Lake 28-core CPU, the new EPYC Milan 7543 CPU is capable of fighting two of them at the same time. In a single-core test, the Intel Xeon configuration scores 5048 points, showing that the new Milan CPU has 20% higher single-core performance, while the multi-core score of the dual Xeon setup is 117171 points, which is 5% faster than AMD CPU. The reason for the higher multi-core score is the sheer number of cores that a dual-CPU configuration offers (32 cores vs 56 cores).

ASRock Rack, a branch of ASRock focused on making server products, has today launched a new motherboard that can accommodate up to 64 core AMD EPYC CPU. Built on the new, proprietary form factor called "Deep Mini-ITX", the ROMED4ID-2T motherboard is just a bit bigger than the standard ITX board. The standard ITX boards are 170 x 170 mm, while this Deep Mini-ITX form extends the board by a bit. It measures 170 x 208.28 mm, or 6.7" x 8.2" for all of the American readers. ASRock specifies that the board supports AMD's second-generation EPYC "Rome" 7002 series processors. Of course, the socket for these CPUs is socket SP3 (LGA4094) with 4094 pins.

The motherboard comes with 4 DDR4 DIMM slots, of any type. Supported DIMM types are R-DIMM, LR-DIMM, and NV-DIMM. If you want the best capacity, LR-DIMM use enables you to use up to 256 GB of memory. When it comes to expansion, you can hook-up any PCIe 4.0 device to the PCIe 4.0 x16 slot. There is also an M.2 2280 key present, so you can fit in one of those high-speed PCIe 4.0 x4 M.2 SSDs. For connection to the outside world, the board uses an Intel X550-AT2 controller that controls two RJ45 10 GbE connectors. There are also two Slimline (PCIe 4.0 x8 or 8 SATA 6 Gb/s), and four Slimline (PCIe 4.0 x8) storage U.2 ports.

According to a report courtesy of Hardwareluxx, where contributor Andreas Schilling reportedly gained access to OEM documentation, AMD's upcoming EPYC Milan CPUs are bound to offer up to 20% performance improvements over the previous EPYC generation. The report claims a 15% IPC performance, paired with an extra 5% added via operating frequency optimization. The report claims that AMD's 64-core designs will feature a lower-clock all-core operating mode, and a 32-core alternate for less threaded workloads where extra frequency is added to the working cores.

Apparently, AMD's approach for the Zen 3 architecture does away with L3 subdivisions according to CCXs; now, a full 32 MB of L3 cache is available for each 8-core Core Compute Die (CCD). AMD has apparently achieved new levels of frequency optimization under Zen 3, with higher upward frequency limits than before. This will see the most benefits in lower core-count designs, as the amount of heat being generated is necessarily lesser compared to more core-dense designs. Milan keeps the same 7 nm manufacturing tech, DDR4, PCIe 4.0, and 120-225 W TDP as the previous-gen Rome. It remains to be seen how these changes actually translate to the consumer versions of Zen 3, Vermeer, later this year.

Intel is preparing to launch its next-generation for server processors and the next in line is the Ice Lake-SP 10 nm CPU. Featuring a Golden Cove CPU and up to 28 cores, the CPU is set to bring big improvements over the past generation of server products called Cascade Lake. Today, thanks to the sharp eye of TUM_APISAK, we have a new benchmark of the Ice Lake-SP platform, which is compared to AMD's EPYC Rome offerings. In the latest GeekBench 4 score, appeared an engineering sample of unknown Ice Lake-SP model with 28 cores, 56 threads, a base frequency of 1.5 GHz, and a boost of 3.19 GHz.

This model was put in a dual-socket configuration that ends up at a total of 56 core and 112 threads, against a single 64 core AMD EPYC 7442 Rome CPU. The dual-socket Intel configuration scored 3424 points in the single-threaded test, where AMD configuration scored notably higher 4398 points. The lower score on Intel's part is possibly due to lower clocks, which should improve in the final product, as this is only an engineering sample. When it comes to the multi-threaded test, Intel configuration scored 38079 points, where the AMD EPYC system did worse and scored 35492 points. The reason for this higher result is unknown, however, it shows that Ice Lake-SP has some potential.

Michael Larabel over at Phoronix posted an extremely comprehensive analysis on the performance differential between AMD's Rome-based EPYC and Intel's Cascade Lake Xeons one-year after release. The battery of tests, comprising more than 116 benchmark results, pits a Xeon Platinum 8280 2P system against an EPYC 7742 2P one. The tests were conducted pitting performance of both systems while running benchmarks under the Ubuntu 19.04 release, which was chosen as the "one year ago" baseline, against the newer Linux software stack (Ubuntu 20.10 daily + GCC 10 + Linux 5.8).

The benchmark conclusions are interesting. For one, Intel gained more ground than AMD over the course of the year, with the Xeon platform gaining 6% performance across releases, while AMD's EPYC gained just 4% over the same period of time. This means that AMD's system is still an average of 14% faster across all tests than the Intel platform, however, which speaks to AMD's silicon superiority. Check some benchmark results below, but follow the source link for the full rundown.

VLSI engineer Fritzchens Fritz, famous for high-detail EM photography of silicon dies and annotations of them, recently published his work on AMD's 7 nm "Renoir" APU silicon. His die-shots were annotated by Nemez aka GPUsAreMagic. The floor-plan of the silicon shows that the CPU component finally dwarfs the iGPU component, thanks to double the CPU cores over the previous-gen "Picasso" silicon, spread over two CCXs (compute complexes). The CCX on "Renoir" is visibly smaller than the one on the "Zen 2" CCDs found in "Matisse" and "Rome" MCMs, as the L3 cache is smaller, at 4 MB compared to 16 MB. Being MCMs with disintegrated memory controllers, it makes more sense for CCDs to have more last-level cache per CCX.

We also see that the iGPU features no more than 8 "Vega" NGCUs, so there's no scope for "Renoir" based desktop APUs to feature >512 stream processors. AMD attempted to compensate for the NGCU deficit by dialing up engine clocks of the iGPU by over 40% compared to those on "Picasso." What caught our eye in the annotation is the PCI-Express physical layer. Apparently the die indeed has 20 PCI-Express lanes besides an additional 4 lanes that can be configured as two SATA 6 Gbps ports thanks to SerDes flexibility.

AMD has scored yet another design win for usage of its high-performance EPYC processors in the Cray Shasta supercomputer. The Cray Shasta will be deployed in the US Navy's Department of Defense Supercomputing Resource Center (DSRC) as part of the High Performance Computing Modernization Program. The peak theoretical computing capability of 12.8 PetaFLOPS, or 12.8 quadrillion floating point operations per second supercomputer will be built with 290,304 AMD EPYC (Rome) processor cores and 112 NVIDIA Volta V100 General-Purpose Graphics Processing Units (GPGPUs). The system will also feature 590 total terabytes (TB) of memory and 14 petabytes (PB) of usable storage, including 1 PB of NVMe-based solid state storage. Cray's Slingshot network will make sure all those components talk to each other at a rate of 200 Gigabits per second.

Navy DSRC supercomputers support climate, weather, and ocean modeling by NMOC, which assists U.S. Navy meteorologists and oceanographers in predicting environmental conditions that may affect the Navy fleet. Among other scientific endeavors, the new supercomputer will be used to enhance weather forecasting models; ultimately, this improves the accuracy of hurricane intensity and track forecasts. The system is expected to be online by early fiscal year 2021.

NVIDIA will soon launch its next-generation lineup of graphics cards based on a new and improved "Ampere" architecture. With the first Tesla server cards that are a part of the Ampere lineup going inside Indiana University Big Red 200 supercomputer, we now have some potential specifications and information about its compute performance. Thanks to the Twitter user dylan552p(@dylan522p), who did some math about the potential compute performance of the Ampere GPUs based on NextPlatform's report, we discovered that Ampere is potentially going to feature up to 18 TeraFLOPs of FP64 compute performance.

With Big Red 200 supercomputer being based on Cray's Shasta supercomputer building block, it is being deployed in two phases. The first phase is the deployment of 672 dual-socket nodes powered by AMD's EPYC 7742 "Rome" processors. These CPUs provide 3.15 PetaFLOPs of combined FP64 performance. With a total of 8 PetaFLOPs planned to be achieved by the Big Red 200, that leaves just a bit under 5 PetaFLOPs to be had using GPU+CPU enabled system. Considering the configuration of a node that contains one next-generation AMD "Milan" 64 core CPU, and four of NVIDIA's "Ampere" GPUs alongside it. If we take for a fact that Milan boosts FP64 performance by 25% compared to Rome, then the math shows that the 256 GPUs that will be delivered in the second phase of Big Red 200 deployment will feature up to 18 TeraFLOPs of FP64 compute performance. Even if "Milan" doubles the FP64 compute power of "Rome", there will be around 17.6 TeraFLOPs of FP64 performance for the GPU.

A prominent Taiwanese newspaper reported that AMD will formally unveil its next-generation "Zen 3" CPU microarchitecture at the 2020 International CES. Company CEO Dr Lisa Su will head an address revealing three key client-segment products under the new 4th generation Ryzen processor family, and the company's 3rd generation EPYC enterprise processor family based on the "Milan" MCM that succeeds "Rome." AMD is keen on developing an HEDT version of "Milan" for the 4th generation Ryzen Threadripper family, codenamed "Genesis Peak."

The bulk of the client-segment will be addressed by two distinct developments, "Vermeer" and "Renoir." The "Vermeer" processor is a client-desktop MCM that succeeds "Matisse," and will implement "Zen 3" chiplets. "Renoir," on the other hand, is expected to be a monolithic APU that combines "Zen 2" CPU cores with an iGPU based on the "Vega" graphics architecture, with updated display- and multimedia-engines from "Navi." The common thread between "Milan," "Genesis Peak," and "Vermeer" is the "Zen 3" chiplet, which AMD will build on the new 7 nm EUV silicon fabrication process at TSMC. AMD stated that "Zen 3" will have IPC increases in line with a new microarchitecture.

AMD is hours away from market-availability and reviews of its 3rd generation Ryzen Threadripper HEDT processors, which includes two models at launch, the 24-core 3960X, and the 32-core 3970X, with prices starting at USD $1,399. The two are closely related to the 2nd generation EPYC "Rome" server processor family, which we know includes core-counts going all the way up to 64. It was hence obvious that a 64-core Threadripper will launch at some point, and that point is 2020, and the part goes by the name 3990X.

The slide detailing the 3990X mentions its core count of 64-core/128-thread, total cache (L2 + L3), which is a staggering 288 MB, and TDP of "just" 280 W. There is no mention of the chip's clock-speeds, and with the 3970X already priced close to $2,000, one can expect even higher prices for a chip with double the core count. At some point these products stop being HEDT and enter the realm of workstations. Intel's short-term response to even the 3970X could be limited to somehow sell the 28-core "Cascade Lake-SP" with quasi-HEDT branding the way it sells the Xeon W-3175X, and on a different platform than the X299.

AMD is preparing to surprise Intel with its 3rd generation Ryzen Threadripper processors derived from the "Rome" MCM (codenamed "Castle Peak" for the client-platform), that features up to 64 CPU cores, a monolithic 8-channel DDR4 memory interface, and 128 PCIe gen 4.0 lanes. For the HEDT platform, AMD could reconfigure the I/O controller die for two distinct sub-platforms within HEDT - one targeting gamers/enthusiasts, and another targeting the demographic that buys Xeon W processors, including the W-3175X. The gamer/enthusiast-targeted processor line could feature a monolithic 4-channel DDR4 memory interface, and 64 PCI-Express gen 4.0 lanes from the processor socket, and additional lanes from the chipset; while the workstation-targeted processor line could essentially be EPYCs, with a wider memory bus width and more platform PCIe lanes; while retaining drop-in backwards-compatibility with AMD X399 (at the cost of physically narrower memory and PCIe I/O).

To support this diverse line of processors, AMD is coming up with not one, but three new chipsets: TRX40, TRX80, and WRX80. The TRX40 could have a lighter I/O feature-set (similar to the X570), and probably 4-channel memory on the motherboards. The TRX80 and WRX80 could leverage the full I/O of the "Rome" MCM, with 8-channel memory and more than 64 PCIe lanes. We're not sure what differentiates the TRX80 and WRX80, but we believe motherboards based on the latter will resemble proper workstation boards in form-factors such as SSI, and be made by enterprise motherboard manufacturers such as TYAN. The chipsets made their way to the USB-IF for certification, and were sniffed out by momomo_us. ASUS is ready with its first motherboards based on the TRX40, the Prime TRX40-Pro, and the ROG Strix TRX40-E Gaming.

AMD invited TechPowerUp to their launch event and editor's day coverage of Zen 2 EPYC processors based on the 7 nm process. The event was a day-long affair which included product demos and tours, and capped off with an official launch presentation which we are able to share with you live as the event goes on. Zen 2 with the Ryzen 3000-series processors ushered in a lot of excitement, and for good reason too as our own reviews show, but questions remained on how the platform would scale to the other end of the market. We already knew, for example, that AMD secured many contracts based on their first-generation EPYC processors, and no doubt the IPC increase and expected increased core count would cause similar, if not higher, interest here. We also expect to know shortly about the various SKUs and pricing involved, and also if AMD wants to shed more light on the future of the Threadripper processor family. Read below, and continue past the break, for our live coverage.21:00 UTC: Lisa Su is on the stage at the Palace of Fine Arts events venue in San Francisco to present AMD's latest developments on EPYC for datacenters, using the Zen 2 microarchitecture.21:10 UTC: AMD focuses not just on delivering a single chip, but it's goal is to deliver a complete solution for the enterprise.

Today an article was posted on Intel's internal employee-only portal called "Circuit News". The post, titled "AMD competitive profile: Where we go toe-to-toe, why they are resurgent, which chips of ours beat theirs" goes into detail about the recent history of AMD and how the company achieved its tremendous growth in recent years. Further, Intel talks about where they see the biggest challenges with AMD's new products, and what the company's "secret sauce" is to fight against these improvements.The full article follows:

TAITRA, the governing body behind the annual Computex trade-show held in Taipei each June, announced that AMD CEO Dr. Lisa Su will host a keynote address which promises to be as exciting as her CES keynote. It is revealed that Dr. Su will simultaneously launch or unveil at least four product lines. High up the agenda is AMD's highly anticipated 3rd generation Ryzen desktop processors in the socket AM4 package, based on "Zen 2" microarchitecture, and a multi-chip module (MCM) codenamed "Matisse." This launch could be followed up by a major announcement related to the company's 2nd generation EPYC enterprise processors based on the "Rome" MCM.

PC enthusiasts are in for a second major announcement, this time from RTG, with a technical reveal or unveiling of Radeon "Navi," the company's first GPU designed from the ground up for the 7 nm silicon fabrication process. It remains to be seen which market-segment AMD targets with the first "Navi" products, and the question on everyone's minds, whether AMD added DXR acceleration, could be answered. Lastly, the company could announce more variants of its Radeon Instinct DNN accelerators.

During the next year and a half, the Finnish IT Center for Science (CSC) will be purchasing a new supercomputer in two phases. The first phase consists of Atos' air-cooled BullSequana X400 cluster which makes use of Intel's Cascade Lake Xeon processors along with Mellanox HDR InfiniBand for a theoretical performance of 2 petaflops. Meanwhile, system memory per node will range from 96 GB up to 1.5 TB with the entire system receiving a 4.9 PB Lustre parallel file system as well from DDN. Furthermore, a separate partition of phase one will be used for AI research and will feature 320 NVIDIA V100 NVLinked GPUs configured in 4-GPU nodes. It is expected that peak performance will reach 2.5 petaflops. Phase one will be brought online at some point in the summer of 2019.

Where things get interesting is in phase two, which is set for completion during the spring of 2020. Atos' will be building CSC a liquid-cooled HDR-connected BullSequana XH2000 supercomputer that will be configured with 200,000 AMD EPYC "Rome" CPU cores which for the mathematicians out there works out to 3,125 64 core AMD EPYC processors. Of course, all that x86 muscle will require a great deal of system memory, as such, each node will be equipped with 256 GB for good measure. Storage will consist of an 8 PB Lustre parallel file system that is to be provided by DDN. Overall phase two will increase computing capacity by 6.4 petaflops (peak). With deals like this already being signed it would appear AMD's next-generation EPYC processors are shaping up nicely considering Intel had this market cornered for nearly a decade.

A SiSoft SANDRA results database entry for a 2P AMD "Rome" EPYC machine sheds light on the lower cache hierarchy. Each 64-core EPYC "Rome" processor is made up of eight 7 nm 8-core "Zen 2" CPU chiplets, which converge at a 14 nm I/O controller die, which handles memory and PCIe connectivity of the processor. The result mentions cache hierarchy, with 512 KB dedicated L2 cache per core, and "16 x 16 MB L3." Like CPU-Z, SANDRA has the ability to see L3 cache by arrangement. For the Ryzen 7 2700X, it reads the L3 cache as "2 x 8 MB L3," corresponding to the per-CCX L3 cache amount of 8 MB.

For each 64-core "Rome" processor, there are a total of 8 chiplets. With SANDRA detecting "16 x 16 MB L3" for 64-core "Rome," it becomes highly likely that each of the 8-core chiplets features two 16 MB L3 cache slices, and that its 8 cores are split into two quad-core CCX units with 16 MB L3 cache, each. This doubling in L3 cache per CCX could help the processors cushion data transfers between the chiplet and the I/O die better. This becomes particularly important since the I/O die controls memory with its monolithic 8-channel DDR4 memory controller.

Intel is reportedly working tirelessly to launch its "Cascade Lake" Xeon Scalable 48-core enterprise processor before year-end, according to a launch window timeline slide leaked by datacenter hardware provider QCT. The slide suggests a late-Q4 thru Q1-2019 launch timeline for the XCC (extreme core count) version of "Cascade Lake," which packs 48 CPU cores across two dies on an MCM. This launch is part of QCT's "early shipment program," which means select enterprise customers can obtain the hardware in pre-approved quantities. In other words, this is a limited launch, but one that's probably enough to upstage AMD's 7 nm EPYC "Rome" 64-core processor launch.

It's only by late-Q1 thru Q2-2019 that the Xeon "Cascade Lake" family would be substantially launched, including lower core-count variants that are still 2-die MCMs. This aligns to preempt or match AMD's 7 nm EPYC family rollout through 2019. "Cascade Lake" is probably Intel's final enterprise microarchitecture to be built on the 14 nm++ node, and consists of 2-die multi-chip modules that feature 48 cores, and a 12-channel memory interface (6-channel per die); with 88-lane PCIe from the CPU socket. The processor is capable of multi-socket configurations. It will also be Intel's launch platform for substantially launching its Optane Persistent Memory product series.