News Posts matching #Willow Cove

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Intel "Tiger Lake" Microarchitecture Features HEDT-like Cache Rebalancing?

With its "Skylake" microarchitecture, Intel significantly re-balanced the cache hierarchy of its HEDT and enterprise multi-core processors to equip CPU cores with larger amounts of faster L2 caches, and lesser amounts on slower shared L3 cache. The company retained its traditional cache balance for its mobile and desktop processor derivatives. This could change with the company's "Tiger Lake" microarchitecture, particularly the "Willow Cove" CPU cores they use, according to a Geekbench online database listing for a prototype quad-core "Tiger Lake-Y" mobile processor.

According to this listing, assuming Geekbench is reading the platform correctly; the "Tiger Lake-Y" processor features a 4-core/8-thread CPU, with a massive 1,280 KB (1.25 MB) of L2 cache per core, and 12 MB of L3 cache. Intel also enlarged the L1D (data) cache to be 48 KB in size, while the L1I (instruction) cache remains 32 KB. This amounts to a 400% increase in L2 cache size, and a 50% increase in L3 cache size. Unlike with "Skylake-X," the increase in L2 cache size doesn't come with a decrease in shared L3 cache size (per core). The "Tiger Lake-Y" processor is being tested on a "Corktown" prototyping platform (a specialized motherboard that has all possible I/O connectivity available with the platform, for testing. "Tiger Lake" is expected to make its debut some time in 2020-21 as a successor to "Ice Lake," and will be built on Intel's refined 10 nm++ silicon fabrication node. Find the Geekbench entry in the source link below.

Intel Scraps 10nm for Desktop, Brazen it Out with 14nm Skylake Till 2022?

In a shocking piece of news, Intel has reportedly scrapped plans to launch its 10 nm "Ice Lake" microarchitecture on the client desktop platform. The company will confine its 10 nm microarchitectures, "Ice Lake" and "Tiger Lake" to only the mobile platform, while the desktop platform will see derivatives of "Skylake" hold Intel's fort under the year 2022! Intel gambles that with HyperThreading enabled across the board and increased clock-speeds, it can restore competitiveness with AMD's 7 nm "Zen 2" Ryzen processors with its "Comet Lake" silicon that offers core-counts of up to 10.

"Comet Lake" will be succeeded in 2021 by the 14 nm "Rocket Lake" silicon, which somehow combines a Gen12 iGPU with "Skylake" derived CPU cores, and possibly increased core-counts and clock speeds over "Comet Lake." It's only 2022 that Intel will ship out a truly new microarchitecture on the desktop platform, with "Meteor Lake." This chip will be built on Intel's swanky 7 nm EUV silicon fabrication node, and possibly integrate CPU cores more advanced than even "Willow Cove," possibly "Golden Cove."

Intel "Tiger Lake" Architecture Combines Willow Cove CPU Cores and Xe iGPU

Even as Intel banks on 10 nm "Ice Lake" to pull it out of the 14 nm dark ages, the company is designing a fascinating new monolithic processor SoC die that succeeds it. Codenamed "Tiger Lake," and slated to debut in 2020, this die packs "Willow Cove" CPU cores and an iGPU based on Intel's Xe architecture, not Gen11. "Willow Cove" CPU cores are more advanced than the "Sunny Cove" cores "Ice Lake" packs, featuring a redesigned on-die cache, additional security features, and transistor optimization yielded from the newer 10 nm+ silicon fabrication process.

Intel is already boasting of 1 TFLOP/s compute power of the Gen11 iGPU on "Ice Lake," so it's logical to predict that the Xe based iGPU will be significantly faster. It will also support the latest display standards. The "next-gen I/O" referenced by Intel could be faster NVMe, Thunderbolt, and USB standards that leverage the bandwidth doubling brought about by PCI-Express gen 4.0. Here's the catch: much like "Ice Lake," the new "Tiger Lake" chip will get a mobile debut as Tiger Lake-Y or Tiger Lake-U, and desktop processors could follow later, possibly even 2021, depending on how much pressure it faces from AMD.

Intel Unveils a Clean-slate CPU Core Architecture Codenamed "Sunny Cove"

Intel today unveiled its first clean-slate CPU core micro-architecture since "Nehalem," codenamed "Sunny Cove." Over the past decade, the 9-odd generations of Core processors were based on incrementally refined descendants of "Nehalem," running all the way down to "Coffee Lake." Intel now wants a clean-slate core design, much like AMD "Zen" is a clean-slate compared to "Stars" or to a large extent even "Bulldozer." This allows Intel to introduce significant gains in IPC (single-thread performance) over the current generation. Intel's IPC growth curve over the past three micro-architectures has remained flat, and only grew single-digit percentages over the generations prior.

It's important to note here, that "Sunny Cove" is the codename for the core design. Intel's earlier codenaming was all-encompassing, covering not just cores, but also uncore, and entire dies. It's up to Intel's future chip-designers to design dies with many of these cores, a future-generation iGPU such as Gen11, and a next-generation uncore that probably integrates PCIe gen 4.0 and DDR5 memory. Intel details "Sunny Cove" as far as mentioning IPC gains, a new ISA (new instruction sets and hardware capabilities, including AVX-512), and improved scalability (ability to increase core-counts without running into latency problems).
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